Cirrus-logic CDB43L22 Manual de usuario

Copyright © Cirrus Logic, Inc. 2007(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS43L22Features Analog Passthrough Input– Four Ster

10 DS792DB1CDB43L223.3 SPDIF In to Mono Speaker OutThe CS43L22’s mono differential PWM speaker output performance can be tested by loading the “SPDIFI

DS792DB1 11CDB43L224. SOFTWARE MODE CONTROLThe CDB43L22 may be used with the Microsoft Windows®-based FlexGUI graphical user interface, allowing soft-

12 DS792DB1CDB43L224.1 Board Configuration TabThe “Board Configuration” tab provides high-level control of signal routing on the CDB43L22. This tab al

DS792DB1 13CDB43L224.2 Passthrough, Power and Serial Audio Interface Configuration TabThe “Passthrough, Power and Serial Audio Interface Configuration

14 DS792DB1CDB43L224.3 DSP Engine TabThe “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the PCM mix vol-ume level a

DS792DB1 15CDB43L224.4 Analog and PWM Output Volume TabThe “Analog and PWM Output Volume” tab provides high-level control of the CS43L22 PWM outputs,H

16 DS792DB1CDB43L224.5 Register Maps TabThe Register Maps tabs provide low-level control of the CS43L22, CS8416, CS8421, FPGA and GPIO reg-ister setti

DS792DB1 17CDB43L225. SYSTEM CONNECTIONS AND JUMPERS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENTVP J35 Input +2.7 V to +5.25 V Power Supply. GND J4 I

18 DS792DB1CDB43L226. JUMPER SETTINGSJMP LABEL PURPOSE POSITION FUNCTION SELECTEDJ31 VLSelects source of voltage for the VL supply*+1.8V Voltage sour

DS792DB1 19CDB43L227. CDB43L22 BLOCK DIAGRAMFigure 9. Block DiagramUSB µ controller CS43L22S/PDIF Input (CS8416)PSIA Input HeaderFPGAOscillator (sock

2 DS792DB1CDB43L22TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

20 DS792DB1CDB43L228. CDB43L22 SCHEMATICSFigure 10. CS43L22 & Analog I/O (Schematic Sheet 1)

DS792DB1 21CDB43L22Figure 11. S/PDIF & Digital Interface (Schematic Sheet 2)

22 DS792DB1CDB43L22Figure 12. Micro & FPGA Control (Schematic Sheet 3)

DS792DB1 23CDB43L22Figure 13. Power (Schematic Sheet 4)

24 DS792DB1CDB43L229. CDB43L22 LAYOUTFigure 14. Silk ScreenCDB43L22CS43L22

DS792DB1 25CDB43L22Figure 15. Top-Side Layer

26 DS792DB1CDB43L22Figure 16. GND (Layer 2)

DS792DB1 27CDB43L22Figure 17. Power (Layer 3)

28 DS792DB1CDB43L22Figure 18. Bottom-Side Layer

DS792DB1 29CDB43L2210.PERFORMANCE PLOTS Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to 20 kHz (unweighted);VA=VD=VA_H

DS792DB1 3CDB43L22Figure 21.THD+N vs. HP Output Power ...

30 DS792DB1CDB43L22-100+0-95-90-85-80-75-70-65-60-55-50-45-40-35-30-25-20-15-10-5dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-140+0-130-120-110-100-90-80-

DS792DB1 31CDB43L2211.REVISION HISTORYRevision ChangesDB1 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inquiries, conta

4 DS792DB1CDB43L221. SYSTEM OVERVIEWThe CDB43L22 platform provides analog and digital interfaces to the CS43L22 and allows for external DSP andI²C® in

DS792DB1 5CDB43L22The CS43L22 is configured using the Cirrus FlexGUI. The device configuration registers are accessible viathe “Register Maps” tab of

6 DS792DB1CDB43L22necting headphones to either output jack, the on-board resistive load should be disconnected by removingthe jumpers on each stake he

DS792DB1 7CDB43L222. QUICK START GUIDEThe following figure is a simplified quick start up guide made for user convenience. The following start up guid

8 DS792DB1CDB43L223. CONFIGURATION OPTIONSIn order to configure the CDB43L22 for making performance measurements, one needs to use Cirrus Logic’s Win-

DS792DB1 9CDB43L223.2 SPDIF In to Stereo Speaker OutThe CS43L22’s stereo differential PWM speaker output performance can be tested by loading the “SPD