Cirrus-logic CS44600 Manual de usuario

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.com6-Channel Digital Amplifier ControllerFeatures > 100 dB Dynamic Range

10 DS633F1CS44600PWM OUTPUT PERFORMANCE CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576

DS633F1 11CS44600PWM FILTER CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM

12 DS633F1CS44600SWITCHING CHARACTERISTICS - SYS_CLK(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF) SWITCHING CHARACTERISTI

DS633F1 13CS44600SWITCHING CHARACTERISTICS - DAI INTERFACE(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 =

14 DS633F1CS44600SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT(VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GN

DS633F1 15CS44600SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Lo

16 DS633F1CS446002. PIN DESCRIPTIONS GNDXTIXTOVLSDAI_MCLKDAI_SCLKSCL/CCLKSDA/CDOUTAD1/CDINAD0/CSINTRSTVDGNDGPIO0GNDVDPPWMOUTB2+VDPGNDPWMOUTA1+PWMO

DS633F1 17CS44600Pin Name Pin # Pin DescriptionPS_SYNC 3Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the switch mode po

18 DS633F1CS44600GPIO3 32General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-ing a RST condition. It can be confi

DS633F1 19CS446002.1 I/O Pin Characteristics Signal NamePower Rail I/O Driver ReceiverRST VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible.SCL/CCLK

2 DS633F1CS44600General DescriptionThe CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample ratec

20 DS633F1CS446003. TYPICAL CONNECTION DIAGRAMS VDPWMOUTA1+PWMOUTA1-PWMOUTB1+PWMOUTB1-VLC0.1 µF+2.5 Vto +5.0 VSCL/CCLKSDA/CDOUTAD1/CDINRST2

DS633F1 21CS44600GNDPSR_DATAPSR_SYNCPSR_MCLKCS4461ADCPower Supply RailPSR_RESETPSR_ENPS_SYNCPower Supply Sync ClockOptionalPWMOUTA1+PWMOUTA1-PWMOUTB1+

22 DS633F1CS446004. APPLICATIONS4.1 OverviewThe CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation,samp

DS633F1 23CS44600• Digital volume control with soft ramp.• Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB

24 DS633F1CS446004.3.1 FsIn Domain ClockingCommon DAI_MCLK frequencies and sample rates are shown in Table 1. 4.3.2 FsOut Domain ClockingTo ensure the

DS633F1 25CS44600 Appropriate clock dividers for each functional block and a programmable divider to support an output forswitched-mode power supp

26 DS633F1CS446004.4 FsIn Clock Domain Modules4.4.1 Digital Audio Input PortThe CS44600 interfaces to an external Digital Audio Processor via the Digi

DS633F1 27CS446004.4.1.1 I²S Data FormatFor I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,and

28 DS633F1CS446004.4.1.3 Right-Justified Data Format In the right-justified format, data is received most significant bit first and with the least sig

DS633F1 29CS446004.4.1.5 One Line Mode #2 In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after aDAI_LRC

DS633F1 3CS44600TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

30 DS633F1CS446004.4.2 Auto Rate DetectThe CS44600 will automatically determine the incoming sample rate, DAI_LRCK, to master clock,DAI_MCLK, ratio an

DS633F1 31CS446004.5 FsOut Clock Domain Modules4.5.1 Sample Rate ConverterOne of the characteristics of a PWM amplifier is that the frequency content

32 DS633F1CS44600ger (addresses 09h - 10h)” on page 58. Volume control changes are programmable to ramp in incrementsof 0.125 dB at a variable rate co

DS633F1 33CS44600 4.5.6 Interpolation FilterThe times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample the data to suppo

34 DS633F1CS446004.5.10 Power Supply Rejection (PSR) Real-Time FeedbackInherent to most Class D power amplifier solutions is the requirement for a cle

DS633F1 35CS446004.6 Control Port Description and TimingThe control port is used to access the registers, allowing the CS44600 to be configured for th

36 DS633F1CS446004.6.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

DS633F1 37CS44600Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Each byte is separat

38 DS633F1CS446005. POWER SUPPLY, GROUNDING, AND PCB LAYOUTThe CS44600 requires a 2.5 V digital power supply for the core logic. In order to support a

DS633F1 39CS44600Figure 28 shows the recommended crystal circuit layout. U1 is the CS44600. C1 and C2 are the VDX power supplydecoupling capacitors. Y

4 DS633F1CS446007.1.1 Increment (INCR) ...

40 DS633F1CS44600Figure 29 shows the recommended PSR circuit layout. See the CS4461 datasheet for further details on the inputbuffer and other associa

DS633F1 41CS446005.1 Reset and Power-UpReliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, andconfi

42 DS633F1CS446006. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and the required ramp speed, to ini

DS633F1 43CS44600 5.1.4 Recommended Power-Down Sequence1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b. 2. When drivin

44 DS633F1CS446006. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 001h ID / Rev. CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV

DS633F1 45CS4460011hChannel Vol. Con-trol 1-FractionCHB2_FVOL1 CHB2_FVOL0 CHA2_FVOL1 CHA2_FVOL0 CHB1_FVOL1 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0page 57

46 DS633F1CS4460021hChnl A3 Comp. Filter - Fine AdjRESERVED RESERVED CHA3_FINE5 CHA3_FINE4 CHA3_FINE3 CHA3_FINE2 CHA3_FINE1 CHA3_FINE0page 61 default

DS633F1 47CS4460032hPWM Minimum Pulse WidthDISABLE_ PWMOUTxx-RESERVED RESERVED MIN_PULSE4 MIN_PULSE3 MIN_PULSE2 MIN_PULSE1 MIN_PULSE0page 67 default 0

48 DS633F1CS446007. REGISTER DESCRIPTIONAll registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD regist

DS633F1 49CS446007.3 Clock Configuration and Power Control (address 02h)7.3.1 Enable SYS_CLK Output (EN_SYS_CLK)Default = 1 Function:This bit enables

DS633F1 5CS446007.20 Interrupt Mode Control (address 28h) ... 6

50 DS633F1CS446007.3.5 Power Down Output Mode (PDN_OUTPUT_MODE)Default = 00 - PWM Outputs are driven low during power down1 - PWM Outputs are driven t

DS633F1 51CS446007.5 Misc. Configuration (address 04h)7.5.1 Digital Interface Format (DIFX)Default = 001Function:These bits select the digital interfa

52 DS633F1CS446007.5.4 De-Emphasis Control (DEM[1:0])Default = 0000 - no de-emphasis01 - 32 kHz de-emphasis filter 10 - 44.1 kHz de-emphasis filter11

DS633F1 53CS446007.7 Volume Control Configuration (address 06h)7.7.1 Single Volume Control (SNGVOL)Default = 0Function:The individual channel volume l

54 DS633F1CS44600trol changes, by the Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur.The MUTE_50/50 bit only d

DS633F1 55CS446007.8 Master Volume Control - Integer (address 07h)7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0])Default = 00000000Function:The

56 DS633F1CS446001. Convert the decimal integer to binary. This is MSTR_IVOL[7:0]. 2. Select the bit representation of the desired 0.25 fractional inc

DS633F1 57CS446007.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh)7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0])Default = 00000

58 DS633F1CS44600 7.13 Channel Mute (address 13h)7.13.1 Independent Channel Mute (CHXX_MUTE)Default = 00 - Disabled1 - EnabledFunction:The PWM outputs

DS633F1 59CS446007.15 Peak Limiter Control Register (address 15h) 7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)Default = 00 - individual channel 1

6 DS633F1CS44600LIST OF FIGURESFigure 1.Performance Characteristics Evaluation Active Filter Circuit ...

60 DS633F1CS44600 7.17 Limiter Release Rate (address 17h) 7.17.1 Release Rate (RRATE[7:0])Default = 00100000Function:The limiter release rate is us

DS633F1 61CS446007.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)7.19.1 Channel Compensation Filter - Fine

62 DS633F1CS446007.20.2 Overflow Level/Edge Select (OVFL_L/E)Default = 0Function:This bit defines the OVFL interrupt type (0 = level sensitive, 1 = ed

DS633F1 63CS446007.22.2 SRC Lock Interrupt (SRC_LOCK)Default = 0Function:When high, indicates that on all active channels, the sample rate converters

64 DS633F1CS446007.23 Channel Over Flow Status (address 2Bh) (Read Only)For all bits in this register, a ‘1’ means the associated condition has occurr

DS633F1 65CS446007.26 GPIO Pin Level/Edge Trigger (address 2Eh)7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)Default = 0Function:General Purpose I

66 DS633F1CS446007.28 GPIO Interrupt Mask Register (address 30h)7.28.1 GPIO Pin Interrupt Mask (M_GPIOX)Default = 0Function:General Purpose Input - Th

DS633F1 67CS44600er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”on page 51 to a 1b. Attempt

68 DS633F1CS44600Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not setwill be ignored.7.31 PWMOUT

DS633F1 69CS44600 7.32 PSR and Power Supply Configuration (address 34h)7.32.1 Power Supply Rejection Enable (PSR_EN)Default = 00 - disable1 - enabl

DS633F1 7CS44600LIST OF TABLESTable 1. Common DAI_MCLK Frequencies ...

70 DS633F1CS446007.32.2 Power Supply Rejection Reset (PSR_RESET)Default = 00 - force reset condition1 - remove reset conditionFunction:This bit is use

DS633F1 71CS446007.33.2 Decimator Scale (DEC_SCALE[18:0])Default = 25868hFunction:These bits are used to scale the power supply reading (Decimator Out

72 DS633F1CS446008. PARAMETER DEFINITIONSDynamic Range (DR)The ratio of the rms value of the signal to the rms sum of all other spectral components ov

DS633F1 73CS44600Signal to Noise Ratio (SNR)SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor

74 DS633F1CS4460010.PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05

DS633F1 75CS4460011.THERMAL CHARACTERISTICS12.ORDERING INFORMATION 13.REVISION HISTORY Parameter Symbol Min Typ Max UnitsJunction to Ambient Thermal I

76 DS633F1CS44600Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one

8 DS633F1CS446001. CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi

DS633F1 9CS44600DC ELECTRICAL CHARACTERISTICS(GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch Rat