Cirrus-logic AN187 Manual de usuario
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1Copyright Cirrus Logic, Inc. 2000(All Rights Reserved)P.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.comA
AN18710 AN187REV16. SILICON LABORATORIES CONTACT INFORMATIONSilicon Laboratories, Inc.4635 Boston LaneAustin, Texas 78735Phone: 1-877-444-3032Email:
• Notes •
AN1872 AN187REV1TABLE OF CONTENTS1. INTRODUCTION ...
AN187AN187REV1 31. INTRODUCTIONAs the world of PDAs and other hand-held devices evolves, more and more of these products desire the support of an anal
AN1874 AN187REV1SCLK is derived from MCLK. It is ½ MCLK. In the default mode, the DAI is in the Master mode. In this mode it generates itsown MCLK clo
AN187AN187REV1 54. INTERFACING THE EP72/7312 TO THE SI3034The EP7312 can generate a 4.096 MHz internal clock. But, in the EP7212, the DAI interface ca
6 AN187REV1AN187Figure 1. Circuit Schematic
7 AN187REV1AN187I236I203I2418I2211I2127I3I4I5I6I7I8I9I10I11I12I13I14I15I16DQI17DQI18DQI19DQI2DQnSCLK_alsonSCLKSCLK_DLYDLRCK_DLYDnFSYNCFigure 2. CPLD
AN1878 AN187REV15. PLD EQUATIONS; SOFTMODEM VIA EP72/7312 DAI TO THE SI3034 DAA CHIP SETP-Terms Fan-in Fan-out Type Name (attributes)Equations1/1 1 1
AN187AN187REV1 92/2 2 1 node N_9N_9 = (N_11 & !N_12 # !N_11 & N_12)Reverse Polarity — !N_9 = (!N_11 & !N_12 # N_11 & N_12)1/2 2 1 node
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