Cirrus-logic CDB4270 Manual de usuario descargar pdf (Pagina 21)

DS686DB3 21

CDB4270

5.3.4 Subclock Routing (Bits 1:0)

Default = 00

Function:

These bits select SCLK and LRCK routing to/from the CS4270, CS8416, CS8406 and the Header. Table 5

shows the available settings

5.4 CS8406 TX CONTROL - ADDRESS 02H

5.4.1 CS8406 OMCLK Divider Control (Bits 7:6)

Default = 00

Function:

These bits select the CS8406 OMCLK divider ratio. Table 6 shows the available settings.

SUB_CK.1 SUB_CK.0 Sub-Clock Routing

- CS4270 is Master

- CS8416 and CS8406 are Slaves to CS4270

- DSP Header Sub-clocks are Outputs from CS4270

- CS4270 and CS8406 are Slaves to CS8416

- CS8416 is Master

- DSP Header Sub-clocks are Outputs from CS8416

- CS4270 is Slave to DSP Header

- CS8416 and CS8406 are Slaves to DSP Header

- DSP Header sub clocks are Inputs

- CS4270 and CS8416 are Slave to CS8406

- CS8406 is Master

- DSP Header Sub-clocks are Outputs from CS8406

Table 5. Sub-Clock Routing

76543210

TXCLK.1 TXCLK.0 Reserved TX_M/S TX_FMT Reserved TXSDIO.1 TXSDIO.0

TXCLK.1 TXCLK.0 CS8406 OMCLK Frequency

0 0 256 x Fs

0 1 128 x Fs

1 0 512 x Fs

1 1 256 x Fs

Table 6. CS8406 OMCLK Frequency

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 49 50

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Cirrus-logic CDB4270 Manual de usuario Pagina 21