Cirrus-logic CS4205 Manual de usuario

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CS420510 DS489PP4AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF l

CS4205DS489PP4 11BIT_CLKTrst_lowTrst2clkTvdd2rst#VddRESET#Figure 1. Power Up TimingFigure 2. Codec Ready from Start-up or Fault ConditionBIT_CLKTsyn

CS420512 DS489PP4BIT_CLKTisetupTiholdTcoSDATA_OUT,SYNCSDATA_INFigure 4. Data Setup and HoldBIT_CLKTs2_pdownSDATA_INSDATA_OUTSYNCWrite to 0x20 Data PR

CS4205DS489PP4 132. GENERAL DESCRIPTIONThe CS4205 is a mixed-signal serial audio codeccompliant with the Intel® Audio Codec ’97 Specifi-cation, revisi

CS420514 DS489PP42.2 Control RegistersThe CS4205 contains a set of AC ’97 compliantcontrol registers, and a set of Cirrus Logic definedcontrol registe

CS4205DS489PP4 15VOLMUTEVOLMUTEVOLMUTEVOL VOLMUTEVOL VOL VOLMUTEBOOSTΣΣ1/2OUTPUTBUFFEROUTPUTBUFFERVOLADCINPUTMUXVOLADCMUTEPCM_OUTPC_BEEPPHONEMIC1MIC2L

CS420516 DS489PP43. DIGITAL SIGNAL PATHSThe CS4205 includes a number of internal digitalsignal path options. Figure 9 shows the principalsignal flow o

CS4205DS489PP4 173.2 Digital Centric ModeDigital centric mode is detailed in Figure 11. In thismode, the analog sources are first mixed in the an-alog

CS420518 DS489PP4 Signal Processing EngineAC-LinkSRCDAC MIXER LINE_OUTLINECDVIDEOAUXMICMONO_OUTΣADC ½ ADCSRC½ SRCI²SIN1I²SIN2I²SIN3ZV ASRC VOLVOLVOLVO

CS4205DS489PP4 194. AC-LINK FRAME DEFINITIONThe AC-link is a bi-directional serial port with dataorganized into frames consisting of one 16-bit andtwe

CS42052 DS489PP4 TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ... 6ANA

CS420520 DS489PP44.1 AC-Link Serial Data Output FrameIn the serial data output frame, data is passed on the SDATA_OUT pin to the CS4205 from the AC ’9

CS4205DS489PP4 214.1.3 Command Data Port (Slot 2)WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an

CS420522 DS489PP44.2 AC-Link Serial Data Input FrameIn the serial data input frame, data is passed on the SDATA_IN pin from the CS4205 to the AC ’97 c

CS4205DS489PP4 234.2.3 Status Data Port (Slot 2)RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the p

CS420524 DS489PP44.3 AC-Link Protocol Violation - Loss of SYNCThe CS4205 is designed to handle SYNC protocolviolations. The following are situations w

CS4205DS489PP4 255. REGISTER INTERFACE Reg Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default00hReset 0 SE4 SE3 SE2 SE1 SE

CS420526 DS489PP4Reg Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default00hPCM Input Volume Mute 0 GL5 GL4 GL3 GL2 GL1 GL0 0 0

CS4205DS489PP4 275.1 Reset Register (Index 00h) SE[4:0] SRS 3D Stereo Enhancement. SE[4:0] = 01001, indicating this feature is present.ID8 18-bit ADC

CS420528 DS489PP45.3 Mono Volume Register (Index 06h)Mute Mono Mute. Setting this bit mutes the MONO_OUT output signal. MM[5:0] Mono Volume Control. T

CS4205DS489PP4 295.5 PC_BEEP Volume Register (Index 0Ah)Mute PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal. PV[3:0] PC_BEEP Volume Con

CS4205DS489PP4 34.2.5 GPIO Pin Status (Slot 12) ... 224.3 AC

CS420530 DS489PP45.7 Microphone Volume Register (Index 0Eh)Mute Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the

CS4205DS489PP4 315.8 Analog Mixer Input Gain Registers (Index 10h - 18h)Mute Stereo Input Mute. Setting this bit mutes the respective input signal, bo

CS420532 DS489PP45.9 Input Mux Select Register (Index 1Ah)SL[2:0] Left Channel Source. The SL[2:0] bits select the left channel source to pass to the

CS4205DS489PP4 335.10 Record Gain Register (Index 1Ch) Mute Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.GL[3:0] Left ADC Gain.

CS420534 DS489PP45.12 General Purpose Register (Index 20h) POP PCM Out Path. When ‘clear’, the PCM out path is mixed pre 3D. When ‘set’, the PCM ou

CS4205DS489PP4 355.14 Powerdown Control/Status Register (Index 26h)EAPD External Amplifier Power Down. The EAPD pin follows this bit and is generally

CS420536 DS489PP45.15 Extended Audio ID Register (Index 28h)ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00,

CS4205DS489PP4 375.16 Extended Audio Status/Control Register (Index 2Ah)PRL Mic ADC Powerdown. When ‘set’, the PRL bit powers down the dedicated Mic A

CS420538 DS489PP45.17 Audio Sample Rate Control Registers (Index 2Ch - 34h) SR[15:0] Sample Rate Select. The Audio Sample Rate Control Registers (Inde

CS4205DS489PP4 395.18 Extended Modem ID Register (Index 3Ch) ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00,

CS42054 DS489PP410.1.3 New Warm Reset ... 5910.1.4 Register

CS420540 DS489PP45.21 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) GP[4:0] GPIO Pin Configuration. This register defines the GPIO input p

CS4205DS489PP4 415.23 GPIO Pin Wakeup Mask Register (Index 52h) GW[4:0] GPIO Pin Wakeup. This register provides a mask for determining if an input GPI

CS420542 DS489PP4CAPS[1:0] L/R Capture Source Select. The CAPS[1:0] bits control the source of data routed to the L/R ADC slots, see Table 14 for actu

CS4205DS489PP4 43Slot Assignment ModeCodec ID Slot MapAMAPSlot AssignmentsID1 ID0 SM1 SM0DACSDOUTSDO2ADCSPDIF for SPDS = 00SPDIF for SPDS = 01LRLRLRLR

CS420544 DS489PP45.26 Misc. Crystal Control Register (Index 60h)DPC DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs

CS4205DS489PP4 455.27 S/PDIF Control Register (Index 68h)SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the SPDO/SDO2 pin. The

CS420546 DS489PP45.28 Serial Port Control Register (Index 6Ah)SDEN Serial Data Output Enable. The SDEN bit enables transmission of serial data on the

CS4205DS489PP4 475.29 Special Feature Address Register (Index 6Ch)A[3:0] Special Feature Address. This register functions as an index register to sele

CS420548 DS489PP45.32 Serial Data Port Volume Control Registers (Index 6Eh, Address 06h - 07h)Mute Serial Data Port Mute. Setting this bit mutes the r

CS4205DS489PP4 495.33 Signal Processing Engine Control Register (Index 6Eh, Address 08h)SDI1M Serial Data Input 1 Mode. The SDI1M bit controls the flo

CS4205DS489PP4 5Figure 25. Line Input (Replicate for Video and AUX)... 64Figure 26. D

CS420550 DS489PP45.34 Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh)EROF Effects Engine Right Channel OverflowELOF E

CS4205DS489PP4 515.35 BIOS-Driver Interface Control Registers (Index 6Eh, Address 0Ch - 0Dh)E[15:0] Event Configuration. The E[15:0] bits control the

CS420552 DS489PP4Default 0000hThe BDI Status Register (Index 7Ah) reflects the state of all possible events. If a bit is ‘0’, the corresponding event

CS4205DS489PP4 535.38 Vendor ID1 Register (Index 7Ch)F[7:0] First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII ‘C

CS420554 DS489PP46. SERIAL DATA PORTS6.1 OverviewThe CS4205 implements two serial data outputports and three serial data input ports that can beused f

CS4205DS489PP4 556.3 Digital DockingThe CS4205 features three serial data input portsused to receive data from three stereo ADCs insidea docking stati

CS420556 DS489PP4SDF[1:0]LRCLKPolarityDataJustificationData Alignment(MSB vs. LRCLK)DataResolutionTiming DiagramRecommended DAC/ADC0 0 negative left j

CS4205DS489PP4 577. ZV PORTThe CS4205 implements an asynchronous serialdata input port that conforms to the Zoomed VideoPort (ZV Port) specification.

CS420558 DS489PP48. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF)The S/PDIF digital output is used to interface theCS4205 to consumer audio equipment extern

CS4205DS489PP4 5910.POWER MANAGEMENT10.1 AC ’97 Reset ModesThe CS4205 supports four reset methods, as de-fined in the AC ’97 Specification: Cold Reset

CS42056 DS489PP4LIST OF TABLESTable 1. AC Mode Control Configurations ...16Table

CS420560 DS489PP410.2 Powerdown ControlsThe Powerdown Control/Status Register(Index 26h) controls the power management func-tions. The PR[5:0] bits i

CS4205DS489PP4 61PR Bit ADCs DACs MixerAnalog ReferenceACLinkInternal Clock Off Mic ADCPR0•PR1 •PR2 ••• •PR3 ••• • •PR4 •PR5 •• ••PRL •Table 25. Power

CS420562 DS489PP411.CLOCKINGThe CS4205 may be operated as a primary or sec-ondary codec. As a primary codec, the systemclock for the AC-link may be ge

CS4205DS489PP4 6322 pF 22 pF24.576 MHzDGNDXTL_OUTXTL_INFigure 24. External Crystal External Clock on XTL_INID1# ID0#AC-Link Timing ModeCodec IDClock

CS420564 DS489PP412.ANALOG HARDWARE DESCRIPTIONThe analog input section consists of four stereoline-level inputs (LINE_L/R, CD_L/GND/R,VIDEO_L/R, and

CS4205DS489PP4 6512.1.3 Microphone Inputs Figure 28 illustrates an input circuit suitable for dy-namic and electret microphones. Electret, alsoknown a

CS420566 DS489PP4ence, nominally 2.4 V. This requires the outputs beAC-coupled to external circuitry (AC loads mustbe greater than 10 kΩ for the line

CS4205DS489PP4 6712.5 Reference DesignSee Section 16 for a CS4205 reference design.

CS420568 DS489PP413. GROUNDING AND LAYOUTFigure 33 on page 69 shows the conceptual layoutfor the CS4205 in XTAL or OSC clocking modes.The decoupling c

CS4205DS489PP4 69 AnalogGroundPin 10.1 µF1000 pFNPO2.2µF0.1 µFY5V0.1 µFY5VY5V0.1 µFY5VAVdd2AVss2AFLT2REFFLTAVss1AVdd1DVdd2AFLT1AFLT3DigitalGroundDV

CS4205DS489PP4 71. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd =

CS420570 DS489PP414. PIN DESCRIPTIONS CS420548 47 46 45 44 43 42 41 40 39 38 37MONO_OUTAVdd2GPIO2/SDI1GPIO3/SDI2GPIO4/SDI3AVss2GPIO0/LRCLKGPIO1/SD

CS4205DS489PP4 71Audio I/O PinsPC_BEEP - Analog Mono Source, Input, Pin 12The PC_BEEP input is intended to allow the PC system POST (Power On Self-Tes

CS420572 DS489PP4VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17These inputs form a stereo input pair to the CS4205. It is intend

CS4205DS489PP4 73AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29This pin needs a 1000 pF NPO capacitor connected to analog ground.AFLT2 -

CS420574 DS489PP4Clock and Configuration PinsXTL_IN - Crystal Input / Clock Input, Pin 2This pin requires either a 24.576 MHz crystal, with the other

CS4205DS489PP4 75This pin is a general purpose I/O pin that can be used to interface with various external circuitry. Whenconfigured as an input, it f

CS420576 DS489PP4These pins provide the supply voltage and ground for the clocking section of the CS4205. In XTAL orOSC clocking modes DVdd1 should be

CS4205DS489PP4 7715.PARAMETER AND TERM DEFINITIONSAC ’97 SpecificationRefers to the Audio Codec ’97 Component Specification Ver 2.1 published by the I

CS420578 DS489PP4Interchannel IsolationThe amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1kHz, 0 dB,

CS4205DS489PP4 7916.REFERENCE DESIGN C17 10uFELEC+R11220kC3322pFNPOC3222pFNPOC90.1uFX7RC231000pFNPOR7 47C220.1uFX7RC15 10uFELEC+C110.1uFX7RJ4PHONO-

CS42058 DS489PP4ANALOG CHARACTERISTICS (Continued) MIXER CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)REC

CS420580 DS489PP417.REFERENCES1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997http://www.cirrus.com/products/papers/meas/me

CS4205DS489PP4 8118.PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.055 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05 0.10 0.15B

CS4205DS489PP4 9DIGITAL CHARACTERISTICS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Parameter Symbol Min Typ Max UnitDVdd = 3.3VLow level input voltage Vil