Cirrus-logic CS4271 Manual de usuario

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCS427124-Bit, 192 kHz Stereo Audio CODECD/A Features! High Per

CS427110 DS592F1DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Notes 3 to 7) Notes: 3. One-half LSB of Triangular PDF dither is added to data.4. Perf

CS4271DS592F1 11DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (Notes 3 to 7) Parameter Symbol Min Typ Max UnitDynamic Performance Dynamic Range 24-B

CS427112 DS592F1DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (Note 12)ParameterFast Roll-OffUnitMin Typ MaxSingle Speed Mode - 4

CS4271DS592F1 13DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE(cont) (Note 12)Notes: 8. Slow Roll-Off interpolation filter is only av

CS427114 DS592F1ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADEMeasurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine

CS4271DS592F1 15ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADEMeasurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine

CS427116 DS592F1ADC DIGITAL FILTER CHARACTERISTICS (Note 17)Notes: 15. The filter frequency response scales precisely with Fs.16. Response sh

CS4271DS592F1 17DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode)Notes: 18. Power Down Mode

CS427118 DS592F1SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Notes: 20. In Co

CS4271DS592F1 19 sdistslrtSDOUTSCLKOutputLRCKOutputSDINsdotsdihtsdistslrtSDOUTSCLKInputLRCKInputSDINsdotsdihtsclkhtsclkltsclkwtFigure

CS42712 DS592F1Stand-Alone Mode Feature Set! System Features– Serial Audio Port Master or Slave Operation– Internal Oscillator for Master Clock!D/A Fe

CS427120 DS592F1 Figure 3. Format 0, Left Justified up to 24-Bit DataLRCKSCLKLeft ChannelRight ChannelSDATA +3 +2 +1LSB+5 +4MSB-1 -2 -3 -4 -5+3 +

CS4271DS592F1 21SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL)Notes: 21. Data must be held for sufficient ti

CS427122 DS592F1SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL)Notes: 22. tspi only needed before first falling ed

CS4271DS592F1 234. TYPICAL CONNECTION DIAGRAM)LJ(I2S/ CS / AD0SDA / CDIN (M1)SCL / CCLK (M0)AINAAINBRSTPower Downand ModeSettings(Control Port)XTIXTOA

CS427124 DS592F15. APPLICATIONS5.1 Stand-Alone Mode5.1.1 Recommended Power-Up Sequence1) When using the CS4271 with an external MCLK, hold RST low unt

CS4271DS592F1 255.1.3.2 Clock Ratio SelectionDepending on the use of an external crystal, or whether the CS4271 is in Master or Slave Mode, differentM

CS427126 DS592F15.1.4 16-Bit Auto-DitherThe CS4271 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCL

CS4271DS592F1 275.2 Control Port Mode5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode1) When using the CS4271 with an external MCLK,

CS427128 DS592F1To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be con-nected to ground and XTO

CS4271DS592F1 29Notes: 26. For the Ratio0 bit listed above, “d” indicates that any value may written.Table 9. Clock Ratios - Control Port Mode Without

CS4271DS592F1 3TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE MODE ... 52.

CS427130 DS592F15.2.4 Internal Digital LoopbackIn Control Port Mode, the CS4271 supports an internal digital loopback mode in which the output of the

CS4271DS592F1 31A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibrationpoint and the CS4

CS427132 DS592F15.4 Analog Connections5.4.1 Input ConnectionsThe analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter

CS4271DS592F1 335.4.2 Output ConnectionsThe recommended output filter configuration is shown in Figure 14. This filter configuration accounts for the

CS427134 DS592F15.5 Mute ControlThe Mute Control pins become active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is in-cor

CS4271DS592F1 356. CONTROL PORT INTERFACEThe Control Port is used to load all the internal settings of the CS4271. The operation of the Control Port m

CS427136 DS592F16.2 I²C ModeIn I²C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock

CS4271DS592F1 377. REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5 4 3 2 1 001h Mo

CS427138 DS592F18. REGISTER DESCRIPTION** All registers are read/write in I²C mode and write only in SPI mode, unless otherwise noted**8.1 Mode Contro

CS4271DS592F1 398.2 DAC Control - Address 02h8.2.1 Auto-Mute (Bit 7)Function:When set, enables the Auto-Mute function. See “Auto-Mute” on page 30.8.2.

CS42714 DS592F16.1 SPI Mode ...

CS427140 DS592F18.2.4 Soft Volume Ramp-Up After Error (Bit 3)Function:An un-mute will be performed after executing a filter mode change, after a MCLK/

CS4271DS592F1 41itored and implemented for each channel. See Table 14 on page 41.Soft Ramp and Zero Cross EnableSoft Ramp and Zero Cross Enable dictat

CS427142 DS592F1 8.4 DAC Channel A Volume Control - Address 04hSee 8.5 DAC Channel B Volume Control - Address 05h8.5 DAC Channel B Volume Control - A

CS4271DS592F1 438.6 ADC Control - Address 06h8.6.1 Dither for 16-Bit Data (Bit 5)Function:When set, this bit activates the Dither for 16-Bit Data feat

CS427144 DS592F18.7.3 Freeze (Bit 2)Function:This function allows modifications to the control port registers without the changes taking effect until

CS4271DS592F1 459. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

CS427146 DS592F110.PACKAGE DIMENSIONSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold m

CS4271DS592F1 4711.APPENDIX 0.4 0.5 0.6 0.7 0.8 0.91120100806040200Frequency(normalized to Fs)Amplitude (dB)0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54

CS427148 DS592F1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.020.0150.010.00500.0050.010.0150.02Frequency(normalized to Fs)Amplitude (dB)0.45

CS4271DS592F1 49 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91120100806040200Frequency(normalized to Fs)Amplitude (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.812010080604020

CS4271DS592F1 51. PIN DESCRIPTIONS - SOFTWARE MODEXTO BMUTECXTI AOUTB-MCLK AOUTB+LRCK AOUTA+SCLK AOUTA-SDOUT AMUTECSDIN FILT+DGND AGNDVD VAVL VQ3SCL/C

CS427150 DS592F1 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.

CS4271DS592F1 51 -140-130-120-110-100-90-80-70-60-50-40-30-20-1000.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Frequency (normalized to Fs)Am

CS427152 DS592F1 -10-9-8-7-6-5-4-3-2-100.40 0.43 0.45 0.48 0.50 0.53 0.55Frequency (normalized to Fs)Amplitude (dB) -0.10-0.08-0.05-0.03

CS4271DS592F1 53Table 18. Revision History Release Date ChangesA1 January 2003 Advance ReleasePP1 March 2003 Preliminary ReleasePP2 October 2003 - Cor

CS42716 DS592F1Pin Name # Pin DescriptionXTOXTI1,2Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate

CS4271DS592F1 72. PIN DESCRIPTIONS - STAND-ALONE MODEXTO BMUTECXTI AOUTB-MCLK AOUTB+LRCK AOUTA+SCLK AOUTA-SDOUT (M/S)AMUTECSDIN FILT+DGND AGNDVD VAVL

CS42718 DS592F1Pin Name # Pin DescriptionXTOXTI1,2Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate

CS4271DS592F1 93. CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condit