Cirrus-logic CS42L51 Manual de usuario Pagina 56
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56 DS679F1
CS42L51
6.7 ADCx Input Select, Invert & Mute (Address 07h)
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See Figure 26.
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
76543210
AINB_MUX1 AINB_MUX0 AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_MUTE ADCA_MUTE
PDN_PGAx AINx_MUX[1:0] Selected Path to ADC
0 00 AIN1x-->PGAx
0 01 AIN2x-->PGAx
0 10 AIN3x/MICINx-->PGAx
0 11 AIN3x/MICINx-->Pre-Amp
(+16/+32 dB Gain)-->PGAx
100AIN1x
101AIN2x
1 10 AIN3x/MICINx
1 11 Reserved
MUX
AIN1x
AIN2x
AIN3x / MICINx
PGA
+16/
32 dB
MUX
AINx_MUX[1:0]
PDN_PGAx
AIN1x
AIN2x
AIN3x
Decoder
ADC
Figure 26. AIN & PGA Selection
- DIGITAL to ANALOG FEATURES 1
- ANALOG to DIGITAL FEATURES 1
- SYSTEM FEATURES 2
- ™ Control) 2
- GENERAL DESCRIPTION 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 5
- LIST OF TABLES 6
- DS679F1 7 7
- 7
- Pin Name # Pin Description 7
- 8 DS679F1 8
- 10 DS679F1 10
- DS679F1 11 11
- ABSOLUTE MAXIMUM RATINGS 12
- SDOUT Code with HPF On 13
- DS679F1 15 15
- VA = 1.8V 16
- 16 DS679F1 16
- VA = 2.5V (nominal) 16
- DS679F1 17 17
- 18 DS679F1 18
- DS679F1 19 19
- 20 DS679F1 20
- DS679F1 21 21
- CONTROL PORT 22
- 24 DS679F1 24
- Parameters Min Typ Max Units 24
- POWER CONSUMPTION 25
- 4. APPLICATIONS 26
- 4.2 Hardware Mode 27
- 4.3 Analog Inputs 28
- DS679F1 29 29
- 2π 50 kΩ()1 µF() 30
- 4.3.6 MIC & PGA Gain 31
- 32 DS679F1 32
- 2.) The ALC maintains 32
- 4.3.8 Noise Gate 33
- 4.4 Analog Outputs 34
- 4.4.1 De-Emphasis Filter 34
- 4.4.2 Volume Controls 35
- 4.4.3 Mono Channel Mixer 35
- 4.4.4 Beep Generator 35
- 4.4.5 Tone Control 36
- 4.4.6 Limiter 36
- DS679F1 37 37
- 4.4.8 On-Chip Charge Pump 38
- 4.5 Serial Port Clocking 38
- 4.5.1 Slave 39
- 4.5.2 Master 39
- 4.6 Digital Interface Formats 40
- 4.7 Initialization 41
- 42 DS679F1 42
- 4.10 Software Mode 43
- 4.10.1 SPI Control 43
- 4.10.2 I²C Control 43
- 44 DS679F1 44
- 4.10.3.1 Map Increment (INCR) 45
- 5. REGISTER QUICK REFERENCE 46
- DS679F1 47 47
- 48 DS679F1 48
- 6. REGISTER DESCRIPTION 49
- 50 DS679F1 50
- Power Down PGA X (PDN_PGAX) 50
- Power Down ADC X (PDN_ADCX) 50
- Power Down (PDN) 50
- Auto-Detect Speed Mode (AUTO) 50
- 52 DS679F1 52
- Master/Slave Mode (M/S) 52
- 6.5 MIC Control (Address 05h) 53
- 6.6 ADC Control (Address 06h) 54
- 56 DS679F1 56
- ADCX Channel Mute (ADCX_MUTE) 56
- 6.9 DAC Control (Address 09h) 58
- 6.18 AOUTx Volume Control: 66
- 74 DS679F1 74
- N CHRG_FREQ[3:0] Frequency 74
- 7. ANALOG PERFORMANCE PLOTS 75
- 76 DS679F1 76
- NOTE: Graph shows the out 76
- DS679F1 77 77
- VA_HP = VA = 1.8 V 77
- 78 DS679F1 78
- 8.1 Auto Detect Enabled 79
- 8.2 Auto Detect Disabled 80
- 9. PCB LAYOUT CONSIDERATIONS 81
- 82 DS679F1 82
- 11.PARAMETER DEFINITIONS 83
- 12.PACKAGE DIMENSIONS 84
- THERMAL CHARACTERISTICS 84
- 13.ORDERING INFORMATION 85
- 14.REFERENCES 85
- 15.REVISION HISTORY 86
- DS679F1 87 87
- Revision Changes 87
- 88 DS679F1 88
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