Cirrus-logic CDB42438 Manual de usuario

Copyright © Cirrus Logic, Inc. 2004(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCDB42438Evaluation Board For CS42438Featuresz Single-ended/Sin

CDB4243810 DS646DB23.2. Internal Sub-Clock RoutingThe graphical description below shows the internal clock routing topology between the CS42438,CS8416

CDB42438DS646DB2 113.3. Internal Data RoutingThe graphical description below shows the internal data routing topology between the CS42438,CS8416, CS84

CDB4243812 DS646DB23.4. Internal TDM Conversion, MUXing and Control (TDMer)The graphical description below shows the routing topology of the TDM conve

CDB42438DS646DB2 133.5 External MCLK ControlSeveral sources for MCLK exist on the CDB42438. The crystal oscillator, Y1, will master theMCLK bus when n

CDB4243814 DS646DB23.6 Bypass Control - AdvancedThe DSP clocks and data may be routed through buffers directly to the CS42438, bypassingthe FPGA. This

CDB42438DS646DB2 154. FPGA REGISTER QUICK REFERENCEFunction 7 6 5 4 3 2 1 001hTDM Conver-sionDSP/CS8416 Reserved Reserved Reserved Reserved Reserved R

CDB4243816 DS646DB25. FPGA REGISTER DESCRIPTIONAll registers are read/write. See the following bit definition tables for bit assignment information. T

CDB42438DS646DB2 175.3 CODEC CLOCK CONTROL (ADDRESS 03H) 5.3.1 MUX (CLK_MUX)Default = 11 Function:This MUX selects the sub-clock lines from the DS

CDB4243818 DS646DB2Function:This MUX selects the data lines from the ADC’s and the external ADC. The last 4 selections are de-multiplexed from the TDM

CDB42438DS646DB2 19is held low for 300 µs whenever this bit changes. 5.5.3 RMCK/LRCK RATIO SELECT (128/256 FS)Default = 00 - 256 Fs1 - 128 FsFunction:

CDB424382 DS646DB2TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

CDB4243820 DS646DB25.6.2 DSP DATA ROUTE TO DAC (DSPDATA->DAC)Default = 10 - Enable1 - DisableFunction:This bit toggles a control line for the data

CDB42438DS646DB2 215.7.2 DSP MCLK (MCLK_M/S)Default = 00 - DSP MCLK is a slave to the MCLK bus.1 - DSP MCLK masters MCLK bus.Function:Enables/disables

CDB4243822 DS646DB25.8 CS5341 AND MISCELLANEOUS CONTROL (ADDRESS 08H)5.8.1 INT MCLK DIVIDE (1.5/2.0 DIVIDE)Default = 00 - Disabled1 - EnabledFunction:

CDB42438DS646DB2 23Function:Selects either I²S or Left Justified interface format for the CS5341. Reset to the CS5341 is toggled. 5.8.6 RESET (‘41_RST

CDB4243824 DS646DB26. HARDWARE MODE Switch S1 configures the CDB42438 in hardware mode. Switch S5 sets up the FPGA and con-trols the routing of all cl

CDB42438DS646DB2 2530011 TDMer w/CS8416 Data (S/PDIF4)1) CS8416 Masters MCLK & PCM Subclocks2) CS8416 data duplicated and Time-Division Multiplexe

CDB4243826 DS646DB2151111 TDMer w/Digital Loopback1) Oscillator Y1 Masters MCLK passed through CS8416. [REMOVE S/PDIF INPUT]2) ADC SDOUT into DAC SDIN

CDB42438DS646DB2 277. CDB CONNECTORS AND JUMPERS CONNECTORReference Designator INPUT/OUTPUT SIGNAL PRESENT+5V J2 Input+5.0 V Power Supply+12V J5

CDB4243828 DS646DB2 JUMPER PURPOSE POSITION FUNCTION SELECTEDJ1 Selects source of voltage for the VA supply +3.3V*+5VVoltage source is +3.3 V regulato

CDB42438DS646DB2 298. CDB BLOCK DIAGRAM CS42438CS8416S/PDIFInputy Differential toSingle-EndedOutputy Single-EndedOutputy Single-Ended toDiff

CDB42438DS646DB2 3LIST OF FIGURESFigure 1. Advanced Register Tab - CS42438 ...

CDB4243830 DS646DB29. CDB SCHEMATICS Figure 8. CS42438

CDB42438DS646DB2 31 Figure 9. DSP Header

CDB4243832 DS646DB2 Figure 10. S/PDIF Input

CDB42438DS646DB2 33 Figure 11. S/PDIF Output

CDB4243834 DS646DB2 Figure 12. FPGA

CDB42438DS646DB2 35 Figure 13. FPGA Connections

CDB4243836 DS646DB2 Figure 14. Control Port

CDB42438DS646DB2 37 Figure 15. Control Port Connections

CDB4243838 DS646DB2 Figure 16. Analog Input 1-2

CDB42438DS646DB2 39 Figure 17. Analog Input 3-4

CDB424384 DS646DB21. SYSTEM OVERVIEW The CDB42438 evaluation board is an excellent means for evaluating the CS42438 CODEC. An-alog and digital audio s

CDB4243840 DS646DB2Figure 18. Analog Input 5

CDB42438DS646DB2 41Figure 19. Analog Input 6

CDB4243842 DS646DB2Figure 20. Analog Input 7-8

CDB42438DS646DB2 43Figure 21. Analog Output 1-2

CDB4243844 DS646DB2Figure 22. Analog Output 3-4

CDB42438DS646DB2 45Figure 23. Analog Output 5-6

CDB4243846 DS646DB2Figure 24. Analog Output 7-8

CDB42438DS646DB2 47Figure 25. Power

CDB4243848 DS646DB210.CDB LAYOUT Figure 26. Silk Screen

CDB42438DS646DB2 49 Figure 27. Top side Layer

CDB42438DS646DB2 5clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface for-mat. Selections are made in the contr

CDB4243850 DS646DB2 Figure 28. Bottom side Layer

CDB42438DS646DB2 5111.REVISION HISTORY Revision Date ChangesDB1 July 2004 Initial ReleaseDB2 OCT 2004 Removed Bill of MaterialsSchematic Changes: Chan

CDB424386 DS646DB2Selections are made in the control port of the FPGA, accessible through the “FPGA” tab ofthe Cirrus Logic FlexGUI software. Refer to

CDB42438DS646DB2 72. SOFTWARE MODEThe CDB42438 is shipped with a Microsoft Windows® based GUI, which allows control over theCS42438 and FPGA registers

CDB424388 DS646DB2Figure 2. Advanced Register Tab - FPGA

CDB42438DS646DB2 93. FPGA SYSTEM OVERVIEWThe FPGA (U16) controls all digital signal routing between the CS42438, CS8406 CS8416,CS5341 and the DSP I/O