Cirrus-logic CRD42L52 Manual de usuario descargar pdf (Pagina 15)

DS680RD1 15

CRD42L52

5. PERFORMANCE PLOTS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band-

width is 20 Hz to 20 kHz (unweighted); VA=VD=VA_HP=1.8 V; Sample Frequency = 48 kHz; HP test load:

L =10kΩ.

Notes:

1. The total harmonic distortion + noise (THD+N) performance of the ADC in the CS42L52 is determined by

the value of the capacitor on the FILT+ pin. Larger capacitor values yield significant improvement in THD+N

at low frequencies. A 1 uF capacitor was used to make the performance measurement in Figure 12.

-100

-97.5

-95

-92.5

-90

-87.5

-85

-82.5

-80

-77.5

-75

-72.5

-70

-67.5

-65

-62.5

-60

-57.5

-55

-52.5

20 20k50 100 200 500 1k 2k 5k 10k

-5

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

-0

+0.5

+1.5

+2.5

+3.5

+4.5

20 20k50 100 200 500 1k 2k 5k 10k

Figure 9. Dynamic Range - Line In to S/PDIF Out Figure 10. Freq. Resp. - Line In to S/PDIF Out

-100

-97.5

-95

-92.5

-90

-87.5

-85

-82.5

-80

-77.5

-75

-72.5

-70

-67.5

-65

-62.5

-60

-57.5

-55

-52.5

20 20k50 100 200 500 1k 2k 5k 10k

Figure 11. THD + N - Line In to S/PDIF Out Figure 12. FFT - S/PDIF In to HP Out @ 0 dBFS

* (Note 1)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k50 100 200 500 1k 2k 5k 10k

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 27 28

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Cirrus-logic CRD42L52 Manual de usuario Pagina 15

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