Cirrus-logic CS2300-CP Manual de usuario

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comFractional-N Clock Multiplier with Internal LCOFeatures Clock Multiplier

CS2300-CP10 DS843F2CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 11.tspi is only needed befo

CS2300-CPDS843F2 114. ARCHITECTURE OVERVIEW4.1 Delta-Sigma Fractional-N Frequency SynthesizerThe core of the CS2300 is a Delta-Sigma Fractional-N Freq

CS2300-CP12 DS843F2 Figure 8. Hybrid Analog-Digital PLLNDigital FilterFrequency Comparator forFrac-N GenerationFrequency Reference Clock Delta-Sigma

CS2300-CPDS843F2 135. APPLICATIONS5.1 Timing Reference ClockThe internal LC oscillator is used to generate the internal timing reference clock (see se

CS2300-CP14 DS843F2Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 LCO cycles (518 ms to634 ms) after CLK_IN is re

CS2300-CPDS843F2 15If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn bit determines whether PLL_OUTcontinues while the PLL re-acquire

CS2300-CP16 DS843F2Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-tem clocks and associated d

CS2300-CPDS843F2 17in either a high resolution (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg bit,with 20.12 being the def

CS2300-CP18 DS843F2Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For exampleif RUD is 1024 an RMOD of 8 wo

CS2300-CPDS843F2 195.4 PLL Clock OutputThe PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.The d

CS2300-CP2 DS843F2TABLE OF CONTENTS1. PIN DESCRIPTION ...

CS2300-CP20 DS843F25.6 Clock Output Stability Considerations5.6.1 Output SwitchingCS2300 is designed such that re-configuration of the clock routing f

CS2300-CPDS843F2 21The control port operates with either the SPI or I²C interface, with the CS2300 acting as a slave device. SPI Modeis selected if th

CS2300-CP22 DS843F2Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 19, the write oper

CS2300-CPDS843F2 236.3 Memory Address PointerThe Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be reador

CS2300-CP24 DS843F28. REGISTER DESCRIPTIONSIn I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only.

CS2300-CPDS843F2 258.2.3 PLL Clock Output Disable (ClkOutDis)This bit controls the output driver for the CLK_OUT pin. 8.3 Device Configuration 1 (Add

CS2300-CP26 DS843F28.3.3 Enable Device Configuration Registers 1 (EnDevCfg1)This bit, in conjunction with EnDevCfg2 and EnDevCfg3, configures the devi

CS2300-CPDS843F2 278.6 Function Configuration 1 (Address 16h)8.6.1 Clock Skip Enable (ClkSkipEn)This bit enables clock skipping mode for the PLL and a

CS2300-CP28 DS843F28.7 Function Configuration 2 (Address 17h)8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl)Defines the state of the PLL output du

CS2300-CPDS843F2 299. CALCULATING THE USER DEFINED RATIONote: The software for use with the evaluation kit has built in tools to aid in calculating an

CS2300-CPDS843F2 38.6.1 Clock Skip Enable (ClkSkipEn) ... 28

CS2300-CP30 DS843F210.PACKAGE DIMENSIONSNotes: 1. Reference document: JEDEC MO-1872. D does not include mold flash or protrusions which is 0.15 mm max

CS2300-CPDS843F2 3111.ORDERING INFORMATION12.REFERENCES1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measure

CS2300-CP32 DS843F2Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one ne

CS2300-CP4 DS843F21. PIN DESCRIPTIONPin Name # Pin DescriptionVD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.G

CS2300-CPDS843F2 52. TYPICAL CONNECTION DIAGRAM GNDSCL/CCLKSDA/CDIN2 kΩFrequency Reference CLK_INCLK_OUTAUX_OUT0.1 µFVD+3.3 VNotes:1. Resistors requi

CS2300-CP6 DS843F23. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 1)Notes:

CS2300-CPDS843F2 7AC ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grad

CS2300-CP8 DS843F2PLL PERFORMANCE PLOTSTest Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; fCLK_OUT= 12.288 MHz; fCLK_IN= 12.2

CS2300-CPDS843F2 9CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMATInputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 10. Data must be held for suff