Cirrus-logic CS4234 Manual de usuario Pagina 73
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DS899F1 73
CS4234
9. PACKAGE DIMENSIONS
Figure 46. Package Drawing
Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and
0.25 mm from the terminal tip.
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A — — 0.0394 — — 1.00 1
A1 0.0000 — 0.0020 0.00 — 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.2362 BSC 6.00 BSC 1
D2 0.1594 .1614 0.1634 4.05 4.10 4.15 1
E 0.2362 BSC 6.00 BSC 1
E2 0.1594 .1614 0.1634 4.04 4.10 4.15 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
eb
A
A1
PIN #1 IDENTIFIER
0.500.10
LASER MAR KING
E
2.00 REF
D2
L
PIN #1 CORNER
2.00 REF
E2
D
40L QFN (6 6 MM BODY) PACKAGE DRAWING
- DAC Features 1
- ADC Features 1
- System Features 1
- Class H Controller Features 1
- Common Applications 1
- General Description 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. PIN DESCRIPTIONS 6
- 1.1 I/O Pin Characteristics 7
- DS899F1 8 8
- ABSOLUTE MAXIMUM RATINGS 9
- TYPICAL CURRENT CONSUMPTION 11
- ANALOG INPUT CHARACTERISTICS 12
- CS4234 AINx 13
- DS899F1 13 13
- CS4234 AINx + 13
- 25000/Fs 14
- ANALOG OUTPUT CHARACTERISTICS 15
- DIGITAL I/O CHARACTERISTICS 17
- DS899F1 19 19
- 4. APPLICATIONS 21
- 4.2.2 Power-down 22
- DS899F1 23 23
- 4.2.3 DAC DC Loading 24
- 4.3 I²C Control Port 25
- 4.3.1.1 Map Increment (INCR) 26
- 4.4 System Clocking 26
- 4.4.1 Master Clock 26
- 4.4.3 Slave Mode Clock Ratios 27
- 4.5 Serial Port Interface 28
- 4.5.1 TDM Mode 28
- 32-Bit Channel Block 29
- 24-Bit Audio Word 29
- 8-Bit Zero Pad 29
- (Or DAC5 Data) 29
- DS899F1 30 30
- 4.6 Internal Signal Path 32
- 4.6.1.1 ADC Signal Routing 32
- 4.6.2 ADC Path 38
- 4.6.2.1 Analog Inputs 38
- 4.6.2.2 ADC HPF 38
- 4.6.3 DAC1-4 Path 39
- 4.6.3.1 De-emphasis Filter 39
- 4.6.4 Low-Latency Path 40
- 4.6.5 DAC5 Path 41
- 4.6.5.4 De-emphasis Filter 42
- 4.6.5.5 Filter Options 42
- 4.6.6 Volume Control 42
- 4.6.6.1 Mute Behavior 43
- 4.6.6.2 Soft Ramp 44
- MIN_DELAY 45
- MAX_DELAY 45
- 4.6.6.3 Noise Gate 46
- 4.7 Reset Line 47
- 4.8.1 Interrupt Masking 47
- DS899F1 49 49
- 5. REGISTER QUICK REFERENCE 50
- DS899F1 51 51
- 6. REGISTER DESCRIPTIONS 52
- 6.3.1 Base Rate Advisory 53
- 6.3.2 Speed Mode 53
- 6.3.3 Master Clock Rate 53
- 6.4.1 Output Sample Width 54
- 6.4.2 Input Sample Width 54
- 6.4.4 DAC5 Sample Width 54
- 7654321 0 55
- 6.6.1 DAC1-4 Data Source 56
- 6.6.2 Low-latency Path Source 56
- 6.7.1 SDIN1 Mask 1 57
- 6.8.1 SDIN1 Mask 2 57
- 6.9.1 SDIN2 Mask 1 58
- 6.10.1 SDIN2 Mask 2 58
- 76543210 59
- 6.11.3 Group Delay 60
- 6.12.1 VA Select 60
- 6.12.3 Invert ADCx 60
- DS899F1 61 61
- Mutes the ADCx signal 61
- Powers down the ADCx path 61
- 6.15.1 DAC1-4 Noise Gate 62
- 6.15.2 DAC1-4 De-emphasis 62
- 6.15.3 DAC5 De-emphasis 62
- 6.19.1 Mute Delay 65
- 6.19.2 Minimum Delay 65
- 6.19.3 Maximum Delay 65
- 6.20.1 x Volume Control 66
- 6.21.1 INT MODE 66
- 6.21.2 Interrupt Pin Polarity 66
- 6.25.1 DACx Clip 69
- 7. ADC FILTER PLOTS 70
- 8. DAC FILTER PLOTS 71
- DS899F1 72 72
- 9. PACKAGE DIMENSIONS 73
- 10.ORDERING INFORMATION 74
- DS899F1 75 75
- 11.1 Voltage Headroom 76
- 11.2 Lead Time 76
- 11.3 Gain Matching 76
- 11.4 SMPS (TPS) Modes 77
- DS899F1 78 78
- 12.REVISION HISTORY 79
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