Cirrus-logic CS5361 Manual de usuario descargar pdf (Pagina 17)

CS5361

DS467F2 17

4.2.2 Master Mode

In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the

master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer

to Table 3 for common master clock frequencies.

÷ 128

÷ 256

÷ 64

M0M1

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 4

÷ 1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 1

MCLK

MDIV

Figure 23. CS5361 Master Mode Clocking

SAMPLE RATE (kHz)

MDIV = 0

MCLK (MHz)

MDIV = 1

MCLK (MHz)

32 8.192 16.384

44.1 11.2896 22.5792

48 12.288 24.576

64 8.192 16.384

88.2 11.2896 22.5792

96 12.288 24.576

176.4 11.2896 22.5792

192 12.288 24.576

Table 3. CS5361 Common Master Clock Frequencies

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 23

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 3
LIST OF TABLES 3
ABSOLUTE MAXIMUM RATINGS 4
HPF enabled 5
8 DS467F2 8
DS467F2 9 9
DIGITAL CHARACTERISTICS 10
THERMAL CHARACTERISTICS 10
12
DS467F2 13 13
2.0 PIN DESCRIPTIONS 14
DS467F2 15 15
4.2 System Clocking 16
4.2.1 Slave Mode 16
4.0 APPLICATIONS 16
4.2.2 Master Mode 17
4.3 Power-up Sequence 18
4.4 Analog Connections 18
4.6 Overflow Detection 19
4.6.1 OVFL Output Timing 19
5.0 PARAMETER DEFINITIONS 20
6.0 PACKAGE DIMENSIONS 21
7.0 REVISION HISTORY 23

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Cirrus-logic CS5361 Manual de usuario Pagina 17

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