Cirrus-logic CS5378 Manual de usuario Pagina 58
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CS5378
DS639F3 58
16.SERIAL DATA INTERFACE
Once digital filtering is complete, each 24-bit out-
put sample is combined with an 8-bit status byte.
These data words are written to an 8-deep FIFO
buffer and then transmitted to the communications
channel through a high speed serial data interface.
16.1 Pin Descriptions
DRDY
- Pin 23
Data ready output signal, active low. Open drain
output requiring an external pull-up resistor.
SCK - Pin 24
Serial clock input.
MISO - Pin 25
Serial data output.
16.2 Serial Data Format
Serial data transactions transfer either 24-bit data
words or 32-bit status+data words, depending on
the STAT bit in the CONFIG register. When trans-
mitting status information, each 8-bit status byte
has an MFLAG bit, a time break bit, and a FIFO
overflow bit encoded as shown in Figure 34.
MFLAG Bit - MFLAG
The MFLAG bit is set in the status byte when an
signal is received on the MFLAG pin. When re-
CS5378
Figure 33. Serial Data Interface Block Diagram
System Telemetry
MISO
DRDY
SCK
Data Ready
Data In
Clock Out
Data
Status
02331
--
MFLAG
-- --
W
31 2930 28 27 26 25 24
Figure 34. 32-bit Serial Data Format
TB
--
--
0 - Modulator Ok
1 - Modulator Error
0 - No Time Break
1 - Time Break
0 - FIFO Ok
1 - FIFO Overflow
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- DS639F3 3 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. GENERAL DESCRIPTION 6
- 1.1 Digital Filter Features 6
- 1.3 System Level Features 7
- 1.4 Configuration Interface 8
- DS639F3 9 9
- SPI Registers 11
- Digital Filter Registers 11
- ABSOLUTE MAXIMUM RATINGS 12
- THERMAL CHARACTERISTICS 13
- DIGITAL CHARACTERISTICS 13
- POWER CONSUMPTION 13
- SWITCHING CHARACTERISTICS 14
- 3. SYSTEM DESIGN WITH CS5378 18
- 3.1 Power Supplies 18
- 3.2 Reset Control 18
- 3.3 PLL and Clock Generation 18
- DS639F3 19 19
- BOOT Reset Mode 21
- 1 EEPROM boot 21
- 0 Microcontroller boot 21
- DS639F3 23 23
- DS639F3 25 25
- Serial Read from EEPROM 26
- DS639F3 27 27
- Sample Command: 28
- Write ROM Coefficients - 0x04 28
- Filter Start - 0x07 28
- DS639F3 29 29
- Table 8. Example EEPROM File 29
- DS639F3 32 32
- Figure 19. SPI Registers 32
- DS639F3 33 33
- DS639F3 34 34
- DS639F3 35 35
- Correction 36
- 10.4 Modulator Data Input 37
- 10.5 Modulator Flag Input 37
- Computation Cycles 39
- Standby Mode 39
- 12.SINC FILTER 40
- 12.1 SINC1 Filter 40
- 12.2 SINC2 Filter 40
- 12.3 SINC3 Filter 40
- SINC filters 41
- DS639F3 43 43
- 13.FIR FILTER 44
- 13.1 FIR1 Filter 44
- 13.2 FIR2 Filter 44
- 13.3 On-Chip FIR Coefficients 45
- SINC + FIR filters 46
- DS639F3 47 47
- Minimum phase group delay 48
- DS639F3 49 49
- Figure 27. FIR1 Coefficients 49
- DS639F3 50 50
- DS639F3 51 51
- 14.IIR FILTER 52
- 14.1 IIR Architecture 52
- 14.2 IIR1 Filter 52
- 14.3 IIR2 Filter 52
- 14.4 IIR3 Filter 53
- 14.5 On-Chip IIR Coefficients 53
- IIR filters 54
- DS639F3 55 55
- DS639F3 56 56
- DS639F3 57 57
- DS639F3 58 58
- DS639F3 59 59
- DS639F3 60 60
- DS639F3 62 62
- DS639F3 63 63
- DS639F3 64 64
- DS639F3 65 65
- 20.REGISTER SUMMARY 66
- 20.1 SPI Registers 66
- DS639F3 67 67
- SPI Address: 0x00 67
- DS639F3 68 68
- SPI Address: 0x03 68
- DS639F3 69 69
- SPI Address: 0x06 69
- DS639F3 70 70
- SPI Address: 0x09 70
- 20.2 Digital Filter Registers 71
- DS639F3 72 72
- DF Address: 0x00 72
- DS639F3 73 73
- DF Address: 0x0E 73
- DS639F3 74 74
- DF Address: 0x20 74
- DS639F3 75 75
- DF Address: 0x21 75
- DS639F3 76 76
- DF Address: 0x25 76
- DF Address: 0x29 77
- DS639F3 77 77
- DS639F3 78 78
- DF Address: 0x2A 78
- DS639F3 79 79
- DF Address: 0x2B 79
- DS639F3 80 80
- DF Address: 0x2C 80
- DS639F3 81 81
- DF Address: 0x2E 81
- DS639F3 82 82
- DF Address: 0x2F 82
- 22.PACKAGE DIMENSIONS 85
- 28L SSOP PACKAGE DRAWING 85
- CS5378-ISZ (Lead Free) 86
- 25.REVISION HISTORY 87
- DS639F3 88 88
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