Cirrus-logic CDB53L30 Manual de usuario

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.comDS963DB1DEC '12Evaluation Board for the CS53L30Features• Analog or d

10 DS963DB1CDB53L304 Software Control Using FlexGUI4 Software Control Using FlexGUIThe Cirrus Logic FlexGUI application is a graphical user interface

11 DS963DB1CDB53L304.3 Using the FlexGUI TabsTo restore one of several standard configurations predefined at the factory, use the Quick Setup drop-dow

12 DS963DB1CDB53L304.3 Using the FlexGUI Tabs4.3.1 Board Config TabThe “Board Config” tab contains the controls for configuring the MCLK source, S/PDI

13 DS963DB1CDB53L304.3 Using the FlexGUI Tabs4.3.2 CS53L30 Config TabThe “CS53L30-1 Config” and “CS53L30-2 Config” tabs contain the controls for confi

14 DS963DB1CDB53L304.3 Using the FlexGUI Tabs4.3.3 CS53L30 ADC TabThe “CS53L30-1 ADC” and “CS53L30-12 ADC” tabs contain the controls for the ADC setti

15 DS963DB1CDB53L304.3 Using the FlexGUI Tabs4.3.4 CS53L30 TDM TabThe “CS53L30-1 TDM” and “CS53L30-2 TDM” tabs contain the controls for configuring th

16 DS963DB1CDB53L304.4 Register Maps Tab4.4 Register Maps TabThe “Register Maps” tab shows the entire user configurable register space for all program

17 DS963DB1CDB53L305 Performance Plots5 Performance Plots Test conditions (unless otherwise specified): FSext=48kHz; MCLKext= 12.2880 MHz; preamp sett

18 DS963DB1CDB53L305 Performance PlotsFigure 5-5. Output FFT, Preamp Setting: +20 dB, PGA Setting: 0 dB, 1 kHz, –1 dBFSFigure 5-6. Output FFT, Preamp

19 DS963DB1CDB53L305 Performance PlotsFigure 5-11. Frequency Response, Notch Filter Disabled, Preamp Enabled (+10 dB or +20 dB), –1 dBFSFigure 5-12. F

2 DS963DB1CDB53L30 Table of Contents1 The CDB53L30 System Overview . . . . . . . . . . . . . . . . . . . . . . . 31.1 Power Supply Circuitry . . .

20 DS963DB1CDB53L305 Performance PlotsFigure 5-17. THD+N (Relative) vs. Frequency, Preamp Setting: 0 dB, –1 dBFSFigure 5-18. THD+N (Relative) vs. Freq

21 DS963DB1CDB53L305 Performance PlotsFigure 5-23. THD+N (Relative) vs. Level, Preamp Setting: +10 dB, PGA Setting: +12 dB, 1 kHzFigure 5-24. THD+N (R

22 DS963DB1CDB53L306 Schematics6 SchematicsFigure 6-1. CS53L30I2C Address: 0x90CS53L30-1I2C Address: 0x92CS53L30-21IN2+2IN2-3IN3+4IN3-5IN4+6IN4-7VA8GN

23 DS963DB1CDB53L306 SchematicsFigure 6-2. InputsCS53L30-1DC Blocki ng CapacitorsCS53L30 InputImpedancePreampSettingDC Bl ocki ngCapacit orHigh-PassCo

24 DS963DB1CDB53L306 SchematicsFigure 6-3. Master Clock PLL and Routing BuffersMas t e r Cl ock PLLI2C Address: 0x9COptional LRCK referenceTo MCLK rou

DS963DB1 25CDB53L306 SchematicsFigure 6-4. Serial Audio Header, Sync I/OMCLK I NSCLKLRCK/FSYNC1.ASP1_SDOUT1.ASP2_SDOUT2.ASP1_SDOUT2.ASP2_SDOUTMCLK OUT

26 DS963DB1CDB53L306 SchematicsFigure 6-5. S/PDIF TransmitterNC1.ASP1_SDOUT1.ASP2_SDOUT2.ASP1_SDOUT2.ASP2_SDOUTSPDIF TransmitterI2C Address: 0x28Coaxi

DS963DB1 27CDB53L306 SchematicsFigure 6-6. MicrocontrollerNSSSCLSDAMOSIRXTXI2CSPISW/HWMicrocontrollerTo MCLKRouting BuffersTo SPDIFSDIN MuxNC1P0.12P0.

28 DS963DB1CDB53L306 SchematicsFigure 6-7. Level Shifters, Control I/O HeaderLevel Shifters and Control I/O Header1.RESET1.INT1.MUTE2.RESET2.INT2.MUTE

DS963DB1 29CDB53L306 SchematicsFigure 6-8. Power SupplyPower Supply Binding Postscurrent sensecurrent senseC244TANT100uF10VTP18+5V12Z4P6SMB6.8AT3G6.8V

3 DS963DB1CDB53L301 The CDB53L30 System Overview1 The CDB53L30 System OverviewThe CDB53L30 evaluation board is a convenient platform for evaluating th

30 DS963DB1CDB53L307 Layout7 Layout Figure 7-1. Assembly Drawing (Top Side)

DS963DB1 31CDB53L307 LayoutFigure 7-2. Layer 1 (Component, Signal—Top)

32 DS963DB1CDB53L307 LayoutFigure 7-3. Layer 2 (Ground)

DS963DB1 33CDB53L307 LayoutFigure 7-4. Layer 3 (+3.3 V, +1.8 V, VP)

34 DS963DB1CDB53L307 LayoutFigure 7-5. Layer 4 (Signal)

DS963DB1 35CDB53L307 LayoutFigure 7-6. Layer 5 (VA)

36 DS963DB1CDB53L307 LayoutFigure 7-7. Layer 6 (Signal—Bottom)

DS963DB1 37CDB53L308 Revision History8 Revision History Release ChangesDB1 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and

4 DS963DB1CDB53L301.4 Serial Audio I/O 1.4 Serial Audio I/OHeader J29 provides an interface for the I2S and TDM serial audio clocks and data. The hea

5 DS963DB1CDB53L301.7 Synchronization I/OThe Serial Audio I/O header J29 provides a MCLK input pin and MCLK output pin. The MCLK IN pin can be used to

6 DS963DB1CDB53L302 Quick-Start Guide2 Quick-Start Guide This section describes a basic setup procedure for the CDB53L30. After completing the steps i

7 DS963DB1CDB53L303 System Connections and Jumper Settings3 System Connections and Jumper SettingsAll power and signal I/O connections are listed in T

8 DS963DB1CDB53L303 System Connections and Jumper SettingsJ34 CONTROL SHORTSGang control signals of CS53L30 #1 and CS53L30 #2ShuntedOpen 1Control sign

9 DS963DB1CDB53L303 System Connections and Jumper SettingsFigure 3-1. CDB53L30 Factory Default Jumper Settings