Cirrus-logic CS61880 Manual de usuario Pagina 60

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CS61880
60 DS450PP3
19.10 Switching Characteristics - Serial Port
Notes: 21. If SPOL = 0, then CS should return high no sooner than 20 ns after the 16
th
rising edge of SCLK during
a serial port read.
Parameter Symbol Min. Typ. Max Unit
SDI to SCLK Setup Time t
dc
-20-ns
SCLK to SDI Hold Time t
cdh
-20-ns
SCLK Low Time t
cl
-50-ns
SCLK High Time t
ch
-50-ns
SCLK Rise and Fall Time t
r
, t
f
-15-ns
CS
to SCLK Setup Time t
cc
-20-ns
SCLK to CS
Hold Time Note 21 t
cch
-20-ns
CS
Inactive Time t
cwh
-70-ns
SDO Valid to SCLK Note 21 t
cdv
-60-ns
CS
to SDO High Z t
cdz
-50-ns
CS
SDI
SCLK
SDO
CLKE=1
LAST ADDR BIT
SDO
CLKE=0
HIGH Z
t
cdv
t
cdv
t
cdz
D0 D1
D0
D6
D1 D6 D7
D7
Figure 23. Serial Port Read Timing Diagram
CS
SCLK
t
cc
SDI
LSB LSB MSB
t
ch
t
cl
t
cch
t
cwh
t
dc
t
cdh
t
cdh
Figure 24. Serial Port Write Timing Diagram
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