Cirrus-logic CS8416 Manual de usuario

Copyright © Cirrus Logic, Inc. 2007(All Rights Reserved)http://www.cirrus.com192 kHz Digital Audio Interface ReceiverFeatures Complete EIAJ CP1201, I

10 DS578F3CS8416SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)Notes:12. If Fs is lower than 46.

DS578F3 11CS8416SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)Notes:15. Data must be held for s

12 DS578F3CS84162. PIN DESCRIPTION - SOFTWARE MODE2.1 TSSOP Pin DescriptionPin NamePin # Pin DescriptionVA 6Analog Power (Input) - Analog power supply

DS578F3 13CS8416RXN 5Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Use

14 DS578F3CS84162.2 QFN Pin DescriptionPin NamePin # Pin DescriptionVA 3Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply shou

DS578F3 15CS8416RXP0RXP1RXP2RXP3RXP4RXP5RXP6RXP7128272678910Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying

16 DS578F3CS84163. PIN DESCRIPTION - HARDWARE MODE3.1 TSSOP Pin DescriptionPin Name Pin # Pin DescriptionVA 6Analog Power (Input) - Analog power suppl

DS578F3 17CS8416OMCK 25System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. When enabled

18 DS578F3CS84163.2 QFN Pin DescriptionPin Name Pin # Pin DescriptionVA 3Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply sho

DS578F3 19CS8416RXN 2Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Use

2 DS578F3CS8416General DescriptionThe CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio dataacco

20 DS578F3CS84164. TYPICAL CONNECTION DIAGRAMSFigure 5. Typical Connection Diagram - Software Mode* A separate analog supply is only necessary in app

DS578F3 21CS8416Figure 6. Typical Connection Diagram - Hardware Mode* These pins must be pulled high to VL or low to DGND through a 47 kΩ resistor.**

22 DS578F3CS84165. APPLICATIONS5.1 Reset, Power-Down and Start-Up When RST is low, the CS8416 enters a low power mode and all internal states are rese

DS578F3 23CS84166. GENERAL DESCRIPTIONThe CS8416 is a monolithic CMOS device that receives and decodes audio data according to the AES3, IEC60958,S/PD

24 DS578F3CS8416clock all the data bits. When in slave mode, the serial audio output port cannot be set for right-justified data. TheCS8416 allows imm

DS578F3 25CS84167.1 Slip/Repeat BehaviorWhen using the serial audio output port in slave mode with an OLRCK input that is asynchronous to theincoming

26 DS578F3CS84167.2 AES11 BehaviorWhen OLRCK is configured as a master, the positive or negative edge of OLRCK (depending on the settingof SOLRPOL in

DS578F3 27CS84168. S/PDIF RECEIVERThe CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encodedaudio and

28 DS578F3CS8416The second output of the input multiplexer is used to provide the selected input as a source to be outputon a GPO pin. This pass throu

DS578F3 29CS84169. GENERAL PURPOSE OUTPUTSThree General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring

DS578F3 3CS8416TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

30 DS578F3CS841610.ERROR AND STATUS REPORTING10.1 GeneralWhile decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to ident

DS578F3 31CS841610.2 Non-Audio DetectionAn AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-coming A

32 DS578F3CS841611.CHANNEL STATUS AND USER-DATA HANDLING“Channel Status Buffer Management” on page 51 describes Channel Status and User data control.1

DS578F3 33CS841612.CONTROL PORT DESCRIPTIONThe control port is used to access the registers, allowing the CS8416 to be configured for the desired oper

34 DS578F3CS841612.2 I²C ModeIn I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. Thereis no CS

DS578F3 35CS841613.CONTROL PORT REGISTER QUICK REFERENCEAddr (HEX)R/WFunction7654321000 R/W Control0 0 FSWCLK 0 0 PDUR TRUNC Reserved Reserved01 R/W C

36 DS578F3CS841614. CONTROL PORT REGISTER DESCRIPTIONS14.1 Memory Address Pointer (MAP) Not a registerMAP[6:0] - Memory Address Pointer. Will automati

DS578F3 37CS84161 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, butincreased wide-band jitter. Use

38 DS578F3CS8416RMCKF – Recovered Master Clock FrequencyDefault = ‘0’0 – RMCK output frequency is 256*FS.1 – RMCK output frequency is 128*FS.CHS – Set

DS578F3 39CS8416 14.5 Control3 (03h)GPO1SEL[3:0] – GPO1 Source select. See “General Purpose Outputs” on page 29.Default = ‘0000’GPO2SEL[3:0] – GPO2 S

4 DS578F3CS841614.4 Control2 (02h) ...

40 DS578F3CS8416TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX sourceDefault =’001’000 – RXP0001 – RXP1, etc14.7 Serial Audio Data Format

DS578F3 41CS8416SOLRPOL - OLRCK clock polarityDefault = ‘0’0 - SDOUT data is valid for the left channel when OLRCK is high.1 - SDOUT data is valid for

42 DS578F3CS841614.11 Receiver Channel Status (0Ah) The bits in this register can be associated with either channel A or B of the received data. The d

DS578F3 43CS8416DTS_CD – DTS_CD data was detected.Reserved – This bit may change state depending on the input audio data.DGTL_SIL – Digital Silence wa

44 DS578F3CS841614.14 Interrupt 1 Status (0Dh) For all bits in this register, a “1” means the associated interrupt condition has occurred at least onc

DS578F3 45CS841614.16 OMCK/RMCK Ratio (18h) This register allows the calculation of the incoming sample rate by the host microcontroller from the e

46 DS578F3CS841615.HARDWARE MODEThe CS8416 has a Hardware Mode that allows the device to operate without a microcontroller. Hardware Mode isselected b

DS578F3 47CS8416each mode, every start-up option select pin (except for TX, which has an internal pull-down) MUST have anexternal pull-up or pull-down

48 DS578F3CS8416Control4 Register (04h)RUN = 1RXD = 0RX_SEL[2] = 0RX_SEL[1:0] = RX_SEL[1:0] pins.TX_SEL[2] = 0TX_SEL[1:0] = TX_SEL[1:0] pins.Serial Au

DS578F3 49CS841616.EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 16.1 AES3 Receiver External ComponentsThe CS8416 AES3 receiver is designed to acce

DS578F3 5CS8416LIST OF FIGURESFigure 1. Audio Port Master Mode Timing ...

50 DS578F3CS8416RXP7RXNRXP0RXP675 Ω.01μ F.01μ F.01μ F...01μ F75 ΩCoax75 Ω75 Ω75 ΩCoax75 ΩCoaxCS8416Figure 18. Consumer Input Circuit Figure 19. S/P

DS578F3 51CS841617.CHANNEL STATUS BUFFER MANAGEMENT17.1 AES3 Channel Status (C) Bit ManagementThe CS8416 contains sufficient RAM to store the first 5

52 DS578F3CS8416ControlPortRegistersFromAES3ReceiverE19 words8-bits 8-bitsABDReceivedDataBuffer5 wordsC Data Serial OutputFigure 21. Channel Status D

DS578F3 53CS841618.PLL FILTER18.1 GeneralAn on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 23is a

54 DS578F3CS841618.2.2 Capacitor SelectionThe type of capacitors used for the PLL filter can have a significant effect on receiver performance. Largeo

DS578F3 55CS841618.2.5 Jitter AttenuationShown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi-mum of

56 DS578F3CS841619.PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0.20 0.3

DS578F3 57CS8416Notes:1. “D” and “E1” are reference datums and do not include mold flash or protrusions, but do include moldmismatch and are measured

58 DS578F3CS841628-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING Notes:1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applie

DS578F3 59CS841620.ORDERING INFORMATIONProduct Description Pb-Free Grade Temp Range Package Container Order#CS8416192 kHz Digital Audio Interface Rece

6 DS578F3CS84161. CHARACTERISTICS AND SPECIFICATIONSAll Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditi

60 DS578F3CS841621.REVISION HISTORYRelease ChangesF1-Reformatted “Features” on page 1-Added RMCK/OMCK maximum in“Switching Characteristics” on page 8.

DS578F3 7CS8416DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Notes:2. Power-Down Mode is defined as RST = LO w

8 DS578F3CS8416SWITCHING CHARACTERISTICS(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes:5. Typical RMS cycle-to-cycle jitter.6. Duty cycle

DS578F3 9CS8416SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)Notes:8. In Software Mode the active edg