Cirrus-logic AN232 Manual de usuario descargar pdf (Pagina 4)

AN232

3. Pin Compatibility

Table 2 shows the pins of the AK5393 and the corresponding pins of the CS5361/81. Please note that the

AK5393 has 28 pins, and the CS5361/81 has 24 pins.

Table 2. Pin Compatibility Between AK5393 and CS5361/81

4. Offset Calibration

The CS5361, CS5381, and AK5393 all have offset calibration capability. However, the calibration process

varies slightly between the AK5393 and the CS5361/CS5381.

4.1 CS5361 and CS5381

The CS5361 and CS5381 implement a high pass filter that can be controlled via the HPF

pin (pin 11). The

high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter.

If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen

and this DC offset will continue to be subtracted from the conversion result.

AK5393 CS5361/81 Description

Pin Number Pin Name Pin Number

Pin Name

1, 28 VREFL, VREFR 24

FILT+

Positive reference voltage

2, 27 GNDL, GNDR 23

REFGND

Ground reference

3, 26 VCOML, VCOMR 22

Internal quiescent reference voltage

4 AINL+ 16

AINL+

Differential Left Channel Input

5 AINL- 17

AINL-

Differential Left Channel Input

6ZCAL -

Zero Calibration Control

7VD 6

Digital power

8DGND 7

GND

Ground reference

9CAL -

Calibration Active Signal

RST

Reset

11 SMODE2 12

I2S/LJ

Serial Audio Interface Format Select

12 SMODE1 2

M/S

Master/Slave Mode Select

13 LRCK 3

LRCK

Left right clock

14 SCLK 4

SCLK

Serial clock

15 SDATA 9

SDOUT

Serial data

16 FSYNC -

Frame Synchronization Signal

17 MCLK 5

MCLK

Master clock

18 DFS 13

Mode Selection

19 HPFE 11

HPF

High Pass Filter Enable

20 TEST -

Test

21 BGND -

Substrate Ground

22 AGND 18

GND

Ground reference

23 VA 19

Analog power

24 AINR- 20

AINR-

Differential Right Channel Input

25 AINR+ 21

AINR+

Differential Right Channel Input

Mode Selection

Logic Power

MDIV

MCLK divider

OVFL

Overflow

1 2 3 4 5 6 7

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