Cirrus-logic AN83 Manual de usuario

1Copyright  Cirrus Logic, Inc. 2001(All Rights Reserved)Cirrus Logic, Inc.P.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581http

AN8310 AN83REV3When the MC68302 generates address 0D00300h,the address seen by the CS8900A will be 00300hwith one of the IO commands (IOR or IOW) acti

AN83AN83REV3 11Status Signals from CS8900AThere are several status signals that are output fromthe CS8900A, such as IOCHRDY, IOCS16,MCS16, etc. In th

AN8312 AN83REV3in BIOS. If the designer intends to use Cirrus sup-plied drivers and does not use an EEPROM or storedriver configuration data in BIOS,

AN83AN83REV3 13LINKACTIVITYD0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15nMWEnMOEA1A2A3nCS2CS8900_RSTD[15:0]A[3:1]CS8900_RSTnURESETEINT3VDDVDDVDDVDDVDD VDDVDD

AN8314 AN83REV3SH3 A2SH3 IRQ0RESETSH3 RO#Chip Select#SH3 WE1#SH3 [D15:D0]SH3 A1SH3 A3RDX-RXD+TXD-TXD+3.3V3.3V3.3V3.3V5100.1uF510CS8900A-CQ33738394041

AN83AN83REV3 15ETHERNET HARDWARE DESIGN FOR EMBEDDED SYSTEMS AND MOTHERBOARDSThis section describes the hardware design of afour-layer, 10BASE-T solut

AN8316 AN83REV3Figure 6. Placement of Components, Top SideCS8900 EVAL REV. BCDB8900B©COPYRIGHT 1994CRYSTAL SEMICONDUCTOR CORPORATIONCS8900 EVAL BOARD

AN83AN83REV3 17Figure 7. Placement of Components, Solder SideCRYSTAL SEMICONDUCTOR CORPORATIONCS8900 EVAL BOARD REV. CP/N CDB8900B

AN8318 AN83REV3PROM is not necessary for the CS8900A, and theCS8900A will respond to IO addresses 0300hthrough 030Fh after a reset.Please refer to the

AN83AN83REV3 19SA00SA01SA02SA03SA04SA05SA06SA07SA08SA09SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19ISA0ISA1ISA2ISA3ISA4ISA5ISA6ISA7ISA8ISA9ISA10ISA11ISA12

AN832 AN83REV3TABLE OF CONTENTSSCHEMATIC CHECKLIST ...

AN8320 AN83REV3 Component Placement and Signal RoutingPlease refer to “Layout Considerations for theCS8900A” on page 35 of this document for moredet

AN83AN83REV3 21LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900This section describes the hardware design of a low-cost, two-layer, full-feature

AN8322 AN83REV3U6CS8900 COMBO EVAL REV. BCDB8900B©COPYRIGHT 1994CRYSTAL SEMICONDUCTOR CORPORATIONCS8900 COMBO EVAL BOARD REV. BP/N CDB8900BC1C2U6U7C10

AN83AN83REV3 23SA00SA01SA02SA03SA04SA05SA06SA07SA08SA09SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19ISA0ISA1ISA2ISA3ISA4ISA5ISA6ISA7ISA8ISA9ISA10ISA11ISA12

AN8324 AN83REV3Figure 14. Power Supply Decoupling SchematicFigure 15. Boot PROM SchematicC19TANT TANT TANT22µF22µF22µFC10 C1++5VGND++SA00SA01SA02SA0

AN83AN83REV3 25Figure 16. AUI SchematicFigure 17. 10BASE-2 SchematicFigure 18. PAL Decode of LA[20-23]+12V0.1µFBSTATUS/HCI12457816151312109AUI_XFR_

AN8326 AN83REV3loaded at the Boot PROM base address register in-dicates the starting location in host memory wherethe Boot PROM is mapped. The Boo

AN83AN83REV3 2710BASE-2 InterfaceA 10BASE-2 transceiver IC, the 83C92C, is usedto generate a 10BASE-2 interface for the referencedesign. Please refer

AN8328 AN83REV3Figure 19. CRD8900 Top-Side Routing

AN83AN83REV3 29Figure 20. CRD8900 Bottom Side Routing

AN83AN83REV3 3LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900 ...21General Description ...

AN8330 AN83REV3Item Reference # Description Quantity Vendor Part NumberBase Configuration: I/O Mode with 10BASE-T Interface1 C5, C7, C8, C11..13, C16

AN83AN83REV3 31Memory ModeIn the memory mode, there are two options wherethe CS8900A can be placed in the ISA memory ad-dress map, lower memory (below

AN8332 AN83REV3face is used to generate the serial data stream onEEDataOut pin (serial data out) with the EESK (se-rial clock). Whenever ELSEL bit is

AN83AN83REV3 33Figure 23 shows a simple PALASMTM programfor the 16R4 PAL that is used in the design shownin Figure 21.;PALASM Design Description;-----

AN8334 AN83REV3Q20 := (Q20 * CS_EL_b) + (/CS_EL_b * SDATA)Q21 := (Q21 * CS_EL_b) + (/CS_EL_b * Q20)Q22 := (Q22 * CS_EL_b) + (/CS_EL_b * Q21)Q23 := (Q2

AN83AN83REV3 35Layout Considerations for the CS8900AThe CS8900A is a mixed signal device having dig-ital and analog circuits for an Ethernet communica

AN8336 AN83REV3U6CS8900 COMBO EVAL REV. BCDB8900B©COPYRIGHT 1994CRYSTAL SEMICONDUCTOR CORPORATIONCS8900 COMBO EVAL BOARD REV. BP/N CDB8900BC1C2U6U7C10

AN83AN83REV3 37Figure 25. Placement of Components, Top SideCS8900 EVAL REV. BCDB8900B©COPYRIGHT 1994CRYSTAL SEMICONDUCTOR CORPORATIONCS8900 EVAL BOAR

AN8338 AN83REV3Figure 26. Placement of Components, Solder SideCRYSTAL SEMICONDUCTOR CORPORATIONCS8900 EVAL BOARD REV. CP/N CDB8900B

AN83AN83REV3 39Figure 2.4.6. Component (top) side of four-layer boardFigure 27. Component (top) side of four-layer board

AN834 AN83REV3SCHEMATIC CHECKLISTBefore getting into the meat of the technical refer-ence manual here is a schematic checklist. It’s pre-sented here,

AN8340 AN83REV3Figure 2.4.7. +5V Plane of four-layer boardFigure 28. +5V Plane of four-layer board

AN83AN83REV3 41Figure 2.4.8. Ground Plane of four-layer boardFigure 29. Ground Plane of four-layer board

AN8342 AN83REV3Figure 2.4.9. Solder side (bottom) of four-layer boardFigure 30. Solder side (bottom) of four-layer board

AN83AN83REV3 43The 20.000 MHz crystal traces should be short,have no via, and run on the component side.Biasing resistor at RES pin of the CS8900A: A

AN8344 AN83REV3mit signal traces should be at least 100 mil. Thiswill provide a good impedance matching for thetransmit and receive circuitry inside

AN83AN83REV3 45able in a 16 pin DIP or 16 pin SOIC package. Seetables 4 and 5 for recommended part numbers.JUMPERLESS DESIGNUsing the CS8900A, both ad

AN8346 AN83REV3ware resets. Therefore, the only information re-quired in the Reset Configuration Block when usedwith Cirrus-provided drivers will be

AN83AN83REV3 47Sheet for additional information on the operation ofthe EEPROM.Driver Configuration InformationThe CS8900A supports random access to 16

AN8348 AN83REV323h Transmission ControlHDX/FDX 15 0 = Half-Duplex, 1 = Full-DuplexReserved 14-7 Reserved for future use, set to 0Ignore Missing Media

AN83AN83REV3 49IEEE Physical AddressThe format of the 48-bit IEEE physical address as expected by the MAC driver is illustrated by the follow-ing exam

AN83AN83REV3 5SOFTWARE CHECKLIST- When servicing the interrupt always read the Interrupt Status Queue (ISQ) first. Process that individual event befo

AN8350 AN83REV3PacketPage Memory BaseBits 15-4 12 MSB of Memory Base Address - The twelve most significant bits of the 24-bit addresslocating the base

AN83AN83REV3 51Adapter Configuration WordBits 15-13 Reserved (set to 0)Bits 12-11 Optimization FlagsUsed to specify the platform’s OS configuration to

AN8352 AN83REV3Manufacturing DateThis word is the adapter’s manufacture date encoded in 16 bits, YR-MO-DY format. (Must be initializedby OEM before s

AN83AN83REV3 53Serial NumberThe two serial number words make up the unique 32-bit OEM serial number for the adapter. Low WordBits 7-0 bits[7-0] of 32-

AN8354 AN83REV3Maintaining EEPROM InformationThe contents of the EEPROM may either be pre-programmed in a stand-alone EEPROM program-mer or programmed

AN83AN83REV3 55ture storing the Driver Configuration Block inBIOS space.OBTAINING IEEE ADDRESSESEach node of a Local Area Network has a uniqueaddress

AN8356 AN83REV3DEVICE DRIVERS AND SETUP/INSTALLATION SOFTWAREThis chapter discusses the software provided byCirrus for use with the CS8900A. That soft

AN83AN83REV3 574) The current configuration of the adapter will bedisplayed. Click on OK or press the Enter keyto proceed.5) Press the ALT key then us

AN836 AN83REV3INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUALThis Technical Reference Manual provides the in-formation which will be helpful in des

AN83AN83REV3 7gram and read the CS8900A control and status reg-isters, and how to transfer user data between theCS8900A and the PC main memory via the

AN838 AN83REV3ISA BusAn ISA bus is a simple, asynchronous bus that caneasily be made to interface to most synchronous orasynchronous buses. An ISA

AN83AN83REV3 9long as the CS8900A contains frames completelyreceived. If ‘n’ words are to be transferred from theCS8900A to the system RAM, the DRQ s