Cirrus-logic CDB42L51 Manual de usuario descargar pdf (Pagina 8)

8 DS679DB2

CDB42L51

2.1 General Configuration Tab

The “General Configuration” tab provides high-level control of signal routing on the CDB42L51. This tab also

includes basic controls for the CS42L51 for quickly setting up the CDB42L51 in simple configurations. Sta-

tus text detailing the CODEC’s specific configuration is shown in parenthesis or appears directly below the

associated control. This text may change depending on the setting of the associated control. A description

of each control group is outlined below:

CODEC Basic Configuration - Includes basic register controls in the CS42L51 used for setting up the inter-

face format, clocking functions and internal analog input routing. See Section 2.2 through Section 2.4 for

more controls in the CS42L51.

S/PDIF Receiver Control - Includes all available hardware mode controls for setting up the CS8415.

S/PDIF Transmitter Control - Includes all available hardware mode controls for setting up the CS8406.

Clock/Data Routing and CODEC Reset - Includes controls used for routing clocks and data between the

CS42L51, CS8415, oscillator and the I/O stake header. Also includes a reset control for the CS42L51.

Update - Reads all registers in the FPGA and CS42L51 and reflects the current values in the GUI.

Reset - Resets FPGA to default routing configuration.

Figure 1. General Configuration Tab

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Cirrus-logic CDB42L51 Manual de usuario Pagina 8