Cirrus-logic CS4340 Manual de usuario descargar pdf (Pagina 12)

CS4340

12 DS297F3

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK

Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.

7. See section 4.2.1 for derived internal frequencies.

Parameters Symbol Min Typ Max Units

MCLK Frequency 1.024 - 25.6 MHz

MCLK Duty Cycle 45 - 55 %

Input Sample Rate Single-Speed Mode

Double-Speed Mode

100

kHz

LRCK Duty Cycle

(Note 6)

SCLK Period

(Note 7) t

sclkw

--s

SCLK rising to LRCK edge

sclkr

--s

SDATA valid to SCLK rising setup time t

sdlrs

--ns

SCLK rising to SDATA hold time

MCLK / LRCK = 512, 256 or 128

sdh

--ns

SCLK rising to SDATA hold time

MCLK / LRCK = 384 or 192

sdh

--ns

SCLK

----------------

sclkw

--------------

512()Fs

----------------------10+

512()Fs

----------------------15+

384()Fs

----------------------15+

SDATA

*INTERNAL SCLK

LRCK

sclkw

sdlrs

sdh

sclkr

Figure 12. Internal Serial Mode Input Timing

The SCLK pulses shown are internal to the CS4340.

SDATA

LRCK

MCLK

*INTERNAL SCLK

Figure 13. Internal Serial Clock Generation

The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 24 25

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Cirrus-logic CS4340 Manual de usuario Pagina 12

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