Cirrus-logic CS4385 Manual de usuario descargar pdf (Pagina 31)

DS671F2 31

CS4385

4.12 Recommended Power-Up Sequence

4.12.1 Hardware Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the

registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.

If RST

can not be held low long enough the SDINx pins should remain static low until all other clocks

are stable, and if possible the RST

should be toggled low again once the system is stable.

2. Bring RST

high. The device will remain in a low power state with FILT+ low and will initiate the

Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

Figure 25. Recommended Mute Circuitry

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Cirrus-logic CS4385 Manual de usuario Pagina 31