Cirrus-logic CS4955 Manual de usuario

1Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)www.cirrus.comCS4954 CS4955NTSC/PAL Digital Video EncoderFeaturesz Six DACs providing simulta

CS4954 CS495510 DS278F6TIMING CHARACTERISTICS(Continued)Parallel Host Port Timing (Figure 27, 28, 29)Symbol Min Typ Max UnitsRead Cycle Time Trd 60 -

CS4954 CS4955DS278F6 112. ADDITIONAL CS4954/5 FEATURES• Five programmable DAC output combinations,including YUV and second composite• Optional pseudo-

CS4954 CS495512 DS278F6The CS4954/5 is designed to function as a videotiming master or video timing slave. In both Masterand Slave Modes, all timing i

CS4954 CS4955DS278F6 13able gain amplifiers in which the chroma amplitudecan be varied via the U_AMP and V_AMP 8-bithost addressable registers.The U a

CS4954 CS495514 DS278F6the six DACs has its own associated DAC enablebit. In the Disable Mode, the 10-bit DACs source(or sink) zero current. When runn

CS4954 CS4955DS278F6 154.12 Teletext ServicesThe CS4954/5 encodes the most common teletextformats, such as European Teletext, World Stan-dard Teletext

CS4954 CS495516 DS278F65.2 Video Timing5.2.1 Slave Mode Input InterfaceIn Slave ITU R.BT601 (not ITU-R.BT656 input)Mode, the CS4954/5 receives signals

CS4954 CS4955DS278F6 17PROG_VS Register (0x0D). VSYNC can be de-layed by thirteen lines or advanced by eighteen lines.5.2.3 Vertical TimingThe CS4954/

CS4954 CS495518 DS278F6VSYNC stays low for 2.5 line-times and transitionshigh with the beginning of line 315. Video input onthe V [7:0] pins is expect

CS4954 CS4955DS278F6 19Field two begins with VSYNC transitioning low atline 266. VSYNC stays low for 3 line cycles andtransitions high during the end

CS4954 CS49552 DS278F6ORDERING INFORMATIONProduct Description Package Pb-Free Grade Temp Range Container Order#CS4954NTSC/PAL Digital Video Encoder48-

CS4954 CS495520 DS278F6As mentioned above, there are no horizontal andvertical timing signals necessary in ITU-R.BT656mode. However in some cases it i

CS4954 CS4955DS278F6 21 5.4 Digital Video Input ModesThe CS4954/5 provides two different digital videoinput modes that are selectable through theIN

CS4954 CS495522 DS278F65.6 Subcarrier GenerationThe CS4954/5 automatically synthesizes NTSCand PAL color subcarrier clocks using the CLK fre-quency an

CS4954 CS4955DS278F6 235.7 Subcarrier CompensationSince the subcarrier is synthesized from CLK, thesubcarrier frequency error will track the clock fre

CS4954 CS495524 DS278F6all 4 bytes to be inserted to the registers and thenenables closed caption insertion and interrupts. Asthe closed caption inter

CS4954 CS4955DS278F6 25TTXRQ provides a fully programmable requestsignal to the teletext source, indicating the insertionperiod of the bitstream at in

CS4954 CS495526 DS278F6order to maintain the strict timing requirements ofthe teletext standard.Table 5 shows how to program the TTXHS registerfor tel

CS4954 CS4955DS278F6 275.13 VBI encodingVBI (Vertical Blanking Interval) encoding is per-formed according to SMPTE RP 188 recommenda-tions. In NTSC mo

CS4954 CS495528 DS278F6tions of GPIO_DATA_REG when it detects regis-ter address 0×0A through the I²C interface. Adetection of address 0×0A can happen

CS4954 CS4955DS278F6 296. FILTER RESPONSES0 1 2 3 4 5 6x 106-70-60-50-40-30-20-1001.3 Mhz. filter frequency responsemagnitude - dBfrequency (Hz)Figure

CS4954 CS4955DS278F6 3TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

CS4954 CS495530 DS278F60 0.5 1 1.5 2 2.5 3 3.5 4 4.55-1-0.8-0.6-0.4-0.200.20.40.60.81Chroma Output Interpolator Pass bandFrequency (MHz)Magnitude Resp

CS4954 CS4955DS278F6 310 2 4 6 8 10 12-3-2.5-2-1.5-1-0.500.51RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) (-3 dB)Frequency (MHz)Magnitude R

CS4954 CS495532 DS278F67. ANALOG7.1 Analog TimingAll CS4954/5 analog timing and sequencing is de-rived from the 27 MHz clock input. The analog out-put

CS4954 CS4955DS278F6 337.4.2 Chrominance DACThe C output pin is driven from a 10-bit 27 MHzcurrent output DAC that internally receives the Cor chromin

CS4954 CS495534 DS278F6current flow from the output. To completely dis-able or for low power device operation, the blueDAC can be totally shut down vi

CS4954 CS4955DS278F6 35must be tied to ground. PDAT [7:0] are available tobe used for GPIO operation in I²C host interfacemode. For 3.3 V operation it

CS4954 CS495536 DS278F6 8.2 Register DescriptionA set of internal registers are available for control-ling the operation of the CS4954/5. The registe

CS4954 CS4955DS278F6 370×09 gpio_ctrl_reg r/w 00h0×0A gpio_data_reg r/w 00h0×0B RESERVED0×0C RESERVED0×0D SYNC_0 r/w 90h0×0E SYNC_1 r/w F4h0×0F I²C_AD

CS4954 CS495538 DS278F6Control Register 0Address 0×00 CONTROL_0 Read/Write Default Value = 01hControl Register 1Address 0×01 CONTROL_1 Read/Write Defa

CS4954 CS4955DS278F6 395CH BWchroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 MHz)4LPF ONchroma lpf on/off (0 = off, 1 = on) 3RGB_BW0 = Full bandwidth on RG

CS4954 CS49554 DS278F67.4.5 Green DAC ...

CS4954 CS495540 DS278F6Control Register 2Address 0×02 CONTROL_2 Read/Write Default Value = 00hBit Number76543210Bit NameOUTPUT FORMAT TTX WST TTX EN S

CS4954 CS4955DS278F6 41Control Register 3Address 0×03 CONTROL_3 Read/Write Default Value = 00hControl Register 4Address 0×04 CONTROL_4 Read/Write Defa

CS4954 CS495542 DS278F6Control Register 5Address 0×05 CONTROL_5 Read/Write Default Value = 00hControl Register 6Address 0×06 CONTROL_6 Read/Write Defa

CS4954 CS4955DS278F6 43Background Color RegisterAddress 0×08 BKG_COLOR Read/Write Default Value = 03hGPIO Control RegisterAddress 0×09 GPIO__REG Read/

CS4954 CS495544 DS278F6Sync Register 1Address 0×0E Sync_1 Read/Write Default Value = F4hI²C Address RegisterAddress 0×0F I²C_ADR Read/Write Default Va

CS4954 CS4955DS278F6 45Hue LSB Adjust RegisterAddress 0×15 HUE_LSB Read/Write Default Value = 00hHue MSB Adjust RegisterAddress 0×16 HUE_MSB Read/Writ

CS4954 CS495546 DS278F6Closed Caption Data RegisterAddress 0×19 CC_21_1 Read/Write Default Value = 00h0×1A CC_21_2 00h0×1B CC_284_1 00h0×1C CC_284_2 0

CS4954 CS4955DS278F6 47Wide Screen Signalling Register 1Address 0×1F WSS_REG_1 Read/Write Default Value = 00hWide Screen Signalling Register 2Address

CS4954 CS495548 DS278F6Filter Register 1Address 0×23 CR_AMP Read/Write Default Value = 80hFilter Register 2Address 0×24 Y_AMP Read/Write Default Value

CS4954 CS4955DS278F6 49Filter Register 5Address 0×27 B_AMP Read/Write Default Value = 80hFilter Register 6Address 0×28 Bright_Offsett Read/Write Defau

CS4954 CS49555 DS278F6LIST OF FIGURESFigure 1. Video Pixel Data and Control Port Timing ...

CS4954 CS495550 DS278F6Teletext Register 2Address 0×2B TTXOVS Read/Write Default Value = 00hTeletext Register 3Address 0×2C TTXOVE Read/Write Default

CS4954 CS4955DS278F6 51Teletext Register 6Address 0×2F TTX_DIS1 Read/Write Default Value = 00hTeletext Register 7Address 0×30 TTX_DIS2 Read/Write Defa

CS4954 CS495552 DS278F6Interrupt Register 0Address 0×32 INT_EN Read/Write Default Value = 00hInterrupt Register 1Address 0×33 INT_CLR Read/Write Defau

CS4954 CS4955DS278F6 539. BOARD DESIGN AND LAYOUT CONSIDERATIONSThe printed circuit layout should be optimized forlowest noise on the CS4954/5 placed

CS4954 CS495554 DS278F6This reduces the total power that the CS4954/5 re-quires, and eliminates the impedance mismatchpresented by an unused connector

CS4954 CS4955DS278F6 55Figure 31. Typical Connection DiagramFerrite BeadL1Vcc1736413839404344484712343718354245151416303126-19272832332988-19101113XT

CS4954 CS495556 DS278F610. PIN DESCRIPTION BCVBSGNDAVAACYV0V1V2V3V4V5V6V7FIELD /CBHSYNC/CBVSYNCINTTESTXTAL_OUTXTAL_INPADRVDDGNDDGNDAVAAGRVREFISETVAAGN

CS4954 CS4955DS278F6 57NOTE: 1. The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not toggle in SLAVE mode

CS4954 CS495558 DS278F611. PACKAGE DRAWINGINCHES MILLIMETERSDIM MIN MAX MIN MAXA --- 0.063 --- 1.60A1 0.002 0.006 0.05 0.15B 0.007 0.011 0.17 0.27D 0.

CS4954 CS4955DS278F6 5912. REVISION HISTORYRevision Date ChangeF1 July 1999 Initial releaseF2 April 2004 Corrected List of FiguresF3 September 2004 Ad

CS4954 CS49556 DS278F61. CHARACTERISTICS AND SPECIFICATIONSABSOLUTE MAXIMUM RATINGSAC & DC PARAMETRIC SPECIFICATIONS (AGND,DGND = 0 V, all voltage

CS4954 CS495560 DS278F6Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the

CS4954 CS4955DS278F6 7Notes: 1. Values are by characterization only2. Output current levels with ISET = 4 kΩ , VREF = 1.232 V.3. DACs are set to low i

CS4954 CS49558 DS278F6AC CHARACTERISTICS Parameter Symbol Min Typ Max UnitsPixel Input and Control Port (Figure 1)Clock Pulse High Time Tch 14.82 18.5

CS4954 CS4955DS278F6 9TIMING CHARACTERISTICS Parameter Symbol Min Typ Max UnitsI²C Host Port Timing (Figure 2)SCL Frequency Fclk 1000 kHzClock Pulse H