Cirrus-logic CS53L30 Manual de usuario Pagina 65
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DS992F1 65
CS53L30
10 Package Dimensions
10 Package Dimensions
10.1 WLCSP Package
Figure 10-1. 30-Ball WLCSP Package Drawing
Table 10-1. WLCSP Package Dimensions
Dim
Dimensions (Millimeters)
Min Nom Max
A 0.450 0.505 0.560
A1 0.170 0.200 0.230
A2 0.280 0.305 0.330
M BSC 2.000 BSC
N BSC 1.600 BSC
b 0.230 0.260 0.290
c REF 0.306 REF
d REF 0.306 REF
e BSC 0.400 BSC
X 2.593 2.613 2.633
Y 2.193 2.213 2.233
ccc = 0.05
ddd = 0.15
WAFER BACK SIDE SIDE VIEW BUMP SIDE
e
N
Y
A
A2
A1
M
X
c
d
Ball A1
Ball A1
Location
Indicator
b
eSeating plane
Ball A1 location indicator
(seen through package)
Z
X
X
øb
Øddd Z X Y
Øccc Z
Notes:
• Dimensioning and tolerances per ASME Y 14.5M–1994.
• The Ball A1 position indicator is for illustration purposes only and may not be to scale.
• Dimension “b” applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating plane
datum Z.
- Analog Input and ADC Features 1
- Digital Processing Features 1
- Digital Output Features 1
- System Features 1
- Applications 1
- General Description 2
- Table of Contents 3
- 1 Pin Descriptions 4
- 1.3 Pin Descriptions 5
- 6 DS992F1 6
- 2 Typical Connection Diagram 7
- 8 DS992F1 8
- 10 DS992F1 10
- DS992F1 11 11
- 12 DS992F1 12
- DS992F1 13 13
- 14 DS992F1 14
- Table 3-11. Specifications—I 14
- DS992F1 15 15
- 16 DS992F1 16
- C Control Port 16
- DS992F1 17 17
- 4 Functional Description 18
- 4.2 Resets 19
- 4.3 Interrupts 19
- 4.4 Capture-Path Inputs 20
- Figure 4-4. Input Gain Paths 21
- Board Chip 22
- 4.4.4 Soft Ramping (DIGSFT) 23
- DMIC_CLK 24
- 4.6 Serial Ports 25
- 4.6.3 High-Impedance Mode 26
- 4.6.4 Master and Slave Timing 26
- DS992F1 27 27
- S Format 28
- 4.7 TDM Mode 29
- 4.7.2 Bursted SCLK 31
- 4.7.3 Transmitting Data 32
- 4.12 MUTE Pin 35
- C Writes with Autoincrement 36
- C Reads with Autoincrement 36
- 5 Systems Applications 37
- Four-Channel Mic Connection 38
- 5.2 Power-Up Sequence 39
- STEP TASK 40
- 5.3 Power-Down Sequence 41
- 5.4 Capture-Path Inputs 42
- Input Signal Level 10 43
- 0.82VA 43
- 5.5 MCLK Jitter 44
- 5.7 Connecting Unused Pins 44
- 6 Register Quick Reference 45
- 7 Register Descriptions 47
- 7.6 MCLK Control 48
- 7.8 Mic Bias Control 49
- 7.10 ASP Control 1 49
- 7.11 ASP TDM TX Control 1–4 50
- 7.12 ASP TDM TX Enable 1–6 50
- 7.13 ASP Control 2 50
- 7.14 Soft Ramp Control 50
- 7.15 LRCK Control 1 51
- 7.16 LRCK Control 2 51
- 7.17 MUTE Pin Control 1 51
- 7.18 MUTE Pin Control 2 51
- 7.19 Input Bias Control 1 52
- 7.20 Input Bias Control 2 52
- 7.21 DMIC1 Stereo Control 52
- 7.22 DMIC2 Stereo Control 52
- 7.23 ADC1/DMIC1 Control 1 52
- 7.24 ADC1/DMIC1 Control 2 53
- 7.25 ADC1 Control 3 53
- 7.26 ADC1 Noise Gate Control 54
- 7.27 ADC1A/1B AFE Control 54
- 7.28 ADC1A/1B Digital Volume 54
- 7.29 ADC2/DMIC2 Control 1 55
- 7.30 ADC2/DMIC2 Control 2 55
- 7.31 ADC2 Control 3 55
- 7.32 ADC2 Noise Gate Control 56
- 7.33 ADC2A/2B AFE Control 56
- 7.34 ADC2A/2B Digital Volume 56
- 7.35 Device Interrupt Mask 57
- 7.36 Device Interrupt Status 57
- 8 Parameter Definitions 58
- DS992F1 59 59
- 9.1 Digital Filter Response 59
- = 50 kHz, Fs 60
- = 16 kHz, MCLK = 19.2 MHz 60
- DS992F1 61 61
- 9.2 PGA Gain Linearity 62
- 9.4 FFTs 63
- 64 DS992F1 64
- 10 Package Dimensions 65
- 11 Thermal Characteristics 66
- 12 Ordering Information 66
- 13 Revision History 67
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