Cirrus-logic CS5480 Manual de usuario Pagina 62
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CS5480
62 DS980F3
6.6.77 Calibration Scale (Scale) – Page18, Address 63
Default = 0x4C CCCC (0.6)
The Scale register is used in the gain calibration to set the level of calibrated results of I-channel RMS. During
gain calibration, the Ix
RMS
results register is divided into the Scale register. The quotient is put into the Ix
GAIN
register. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of
the MSB. Negative values are not used.
6.6.78 V-channel Zero-crossing Threshold (VZX
LEVEL
) – Page 18, Address 58
Default = 0x10 0000 (0.125)
VZX
LEVEL
is the level that the peak instantaneous voltage must exceed for the zero-crossing detection to
function. This is a two's complement value in the range of -1.0
value<1.0, with the binary point to the right of
the MSB. Negative values are not used.
6.6.79 I-channel Zero-crossing Threshold (IZX
LEVEL
) – Page 18, Address 24
Default = 0x10 0000 (0.125)
IZX
LEVEL
is the level that the peak instantaneous current must exceed for the zero-crossing detection to func-
tion. This is a two's complement value in the range of -1.0
value<1.0, with the binary point to the right of the
MSB. Negative values are not used.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- DS980F3 3 3
- LIST OF FIGURES 4
- LIST OF TABLES 4
- 1. OVERVIEW 5
- 2. PIN DESCRIPTION 6
- 2.1 Analog Pins 7
- 176.78 mV 7
- 2.2 Digital Pins 7
- 2.2.3.1 SPI 8
- 2.2.3.2 UART 8
- 2.2.4 MODE Pin 8
- TYPICAL LOAD PERFORMANCE 9
- 10 DS980F3 10
- Figure 6. I 10
- Load Performance 10
- ANALOG CHARACTERISTICS 11
- VOLTAGE REFERENCE 12
- DIGITAL CHARACTERISTICS 13
- SWITCHING CHARACTERISTICS 14
- DS980F3 15 15
- ABSOLUTE MAXIMUM RATINGS 16
- 4. SIGNAL FLOW DESCRIPTION 17
- 4.4 Phase Compensation 18
- 4.7 Digital Integrators 18
- 4.8 Low-rate Calculations 18
- sources 19
- 5.1 Power-on Reset 21
- 5.2 Power Saving Modes 21
- 5.3 Zero-crossing Detection 21
- (Config2) 23
- MCFG[1:0] 23
- 5.7 Energy Pulse Generation 25
- Overcurrent Detection 26
- 5.9 Phase Sequence Detection 27
- 5.10 Temperature Measurement 27
- 5.11 Anti-Creep 28
- 5.12 Register Protection 28
- 6.1 Host Commands 29
- 6.1.3 Checksum 30
- 6.1.4 Serial Time Out 30
- Y Y 0x D5 3998 34
- 6.6 Register Descriptions 37
- ) – Page 0, Address 55 43
- ) – Page 18, Address 58 62
- ) – Page 18, Address 24 62
- 7. SYSTEM CALIBRATION 63
- 7.2 Phase Compensation 64
- (OWR) sample 65
- 8. BASIC APPLICATION CIRCUITS 66
- DS980F3 67 67
- 9. PACKAGE DIMENSIONS 68
- 10. ORDERING INFORMATION 69
- 12. REVISION HISTORY 69
- 70 DS980F3 70
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