Cirrus-logic EP93xx Manual de usuario descargar pdf (Pagina 158)

100

101

5-32 DS785UM1

System Controller

EP93xx User’s Guide

SDIV: SCLK divide select.

1 - SCLK = MCLK / 4,

0 - SCLK = MCLK / 2.

MENA: Enable master clock generation.

ESEL: External clock source select.

0 - Use the external XTALI clock input as the clock source.

1 - Use one of the internal PLLs selected by PSEL as the

clock source.

PSEL: PLL source select.

1 - Select PLL2 as the clock source.

0 - Select PLL1 as the clock source.

PDIV: Pre-divider value. Generates divide by 2, 2.5, or 3 from the

clock source.

00 - Disable clock

01 - Divide-by-2

10 - Divide-by-2.5

11 - Divide-by-3

MDIV: MCLK divider value. Forms a divide-by-N of the pre-divide

clock output. MCLK is the source clock divided by PDIV

divided by N.

KeyTchClkDiv

Address:

0x8093_0090 - Read/Write, Software locked

Default:

0x0000_0000

Definition:

Configures the Key Matrix, Touchscreen, and ADC clocks. Touchscreen clock

is a fixed divide-by-4 from the ADC clock. Touch Filter clock is a fixed divide-

by-2 from the ADC clock.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

TSEN: Touchscreen and ADC clock enable

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TSEN RSVD ADIV

1514131211109876543210

KEN RSVD KDIV

1 2 ... 153 154 155 156 157 158 159 160 161 162 163 ... 823 824

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Cirrus-logic EP93xx Manual de usuario Pagina 158

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