Cirrus-logic AN339 Manual de usuario descargar pdf (Pagina 9)

AN339

AN339REV1

AN339REV1 9

7. JITTER MEASUREMENT TO DAC THD+N CORRELATION

The results presented in Section 5 show that the amount of baseband jitter present on the recovered master clock

of each receiver is reduced as the sample rate of the input S/PDIF signal is increased. This relationship is a direct

result of the increased phase detector update rate, which is proportional to the incoming sample rate.

Also, the results of Section 6 show that baseband jitter present on the recovered master clock has the most signifi-

cant affect on the converter’s THD+N performance when its audio input signal level and frequency are both high.

Using this information, a simple test was devised to help correlate the level of baseband jitter to the DAC’s THD+N.

To do this, a S/PDIF signal with a fixed 0 dBFS, 18 kHz audio tone was transmitted into both receivers. The sample

rate of the S/PDIF signal was then varied, and both the recovered clock baseband jitter and the THD+N of the

CS4398 were measured at each sample rate step. The results are shown in Figure 30 and Figure 31 below.

The plots confirm the relationship between recovered clock baseband jitter and DAC THD+N. It can again be seen

that the baseband jitter and THD+N for the CS8416 when PDUR = 1 is better than that with the CS8414. For sample

rates greater than 96 kHz (up to 192 kHz), the jitter and THD+N for the CS8416 with PDUR = 0 is comparable to the

performance of the CS8414 with a sample rate of 48 kHz.

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Figure 28. FFT - -60 dBFS, 997 Hz

Fs = 192 kHz

Figure 29. FFT - No Input (w/ Dither)

Out of Band, Fs = 192 kHz

CS8414 (48 kHz)

CS8416 PDUR=0

CS8414 (48 kHz)

CS8416 PDUR=0

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Baseband Jitter (ps)

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18 kHz THD+N (dBr)

Figure 30. Baseband Jitter vs Sample Rate

Figure 31. THD+N vs Sample Rate

CS8414

CS8416 PDUR=0

CS8416 PDUR=1

CS8414

CS8416 PDUR=0

CS8416 PDUR=1

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Cirrus-logic AN339 Manual de usuario Pagina 9

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