Cirrus-logic CDB5376 Manual de usuario descargar pdf (Pagina 36)

CDB5376

36 DS612DB3

modulators are 4-wire INR+, INF+, INF-, INR- quad groups, and are routed with INF+ and INF- as a tra-

ditional differential pair and INR+ and INR- as guard traces outside the respective INF+ and INF- traces.

2.5.3 Bypass Capacitors

Each device power supply pin includes 0.1 µF bypass capacitors placed as close as possible to the pin

on the back side of the PCB. Each power supply net includes at least 100 µF bulk capacitance as a charge

well for transient current loads.

Figure 5. Quad Group Routing

INR+

INF+

INF-

INR-

INR+

INF+

INF-

INR-

Figure 6. Bypass Capacitor Placement

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1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 79 80

Features 1
General Description 1
REVISION HISTORY 2
TABLE OF CONTENTS 3
LIST OF FIGURES 5
LIST OF TABLES 6
1. INITIAL SETUP 7
1.1 Kit Contents 7
1.2 Hardware Setup 7
1.2.1 Default Jumper Settings 8
DS612DB3 11 11
12 DS612DB3 12
1.4 Self-testing CDB5376 13
1.4.1 Noise test 13
1.4.2 Distortion Test 14
DS612DB3 15 15
2.2.1 Analog Inputs 16
2.2 Analog Hardware 16
2.2.1.4 Input Protection 17
2.2.1.5 Input RC Filters 17
2.2.1.6 Common Mode Bias 18
DS612DB3 19 19
2.2.2.3 Anti-alias RC Filters 20
2.2.3.2 Offset Enable - OFST 21
2.2.5.2 Common Mode Bias 22
2.3 Digital Hardware 23
2.3.1 Digital Filter 23
24 DS612DB3 24
2.3.2 Interface CPLD 25
26 DS612DB3 26
DS612DB3 27 27
28 DS612DB3 28
2.3.5 Phase Locked Loop 29
Specification Value 30
Supply Voltage, Current 30
3.3 V, 10 µA 30
2.3.6.1 CLK, SYNC 31
2.3.6.2 I 32
C - SCL, SDA, Bypass 32
2.3.8 External Connector 33
2.4 Power Supplies 33
34 DS612DB3 34
2.5 PCB Layout 35
2.5.1 Layer Stack 35
2.5.2 Differential Pairs 35
2.5.3 Bypass Capacitors 36
2.5.4 Dual Row Headers 37
3. SOFTWARE DESCRIPTION 38
3.1 Menu Bar 38
3.2 About Panel 39
3.3 Setup Panel 40
3.3.1 USB Port 41
3.3.2 Digital Filter 42
3.3.3 Analog Front End 43
3.3.4 Test Bit Stream 43
3.3.5 Gain/Offset 44
3.3.6 Data Capture 45
3.3.7 External Macros 46
• M1 = . /macros/m1.mac 46
• M2 = . /macros/m2.mac 46
3.4 Analysis Panel 47
3.4.1 Test Select 48
3.4.2 Statistics 49
3.4.3 Plot Enable 49
50 DS612DB3 50
3.5 Control Panel 51
3.5.1 DF Registers 52
3.5.2 DF Commands 52
3.5.3 SPI 52
3.5.4 Macros 53
3.5.5 GPIO 53
3.5.6 Customize 54
3.5.7 External Macros 54
4. BILL OF MATERIALS 55
56 DS612DB3 56
DS612DB3 57 57
5. LAYER PLOTS 58
DS612DB3 59 59
60 DS612DB3 60
DS612DB3 61 61
62 DS612DB3 62
DS612DB3 63 63
64 DS612DB3 64
DS612DB3 65 65
6. SCHEMATICS 66
DS612DB3 67 67
68 DS612DB3 68
DS612DB3 69 69
70 DS612DB3 70
DS612DB3 71 71
72 DS612DB3 72
DS612DB3 73 73
74 DS612DB3 74
DS612DB3 75 75
76 DS612DB3 76
DS612DB3 77 77
78 DS612DB3 78
DS612DB3 79 79
80 DS612DB3 80

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Cirrus-logic CDB5376 Manual de usuario Pagina 36

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