Cirrus-logic CS42518 Manual de usuario Pagina 79

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 91
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 78
DS584F2 79
CS42518
10.1.2 Jitter Attenuation
Figures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range when
used with the external PLL component values and locking modes as specified in Table 21.
The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than
32 kHz or for locking to the SAI_LRCK input. These specifications state a maximum of 2 dB jitter gain or
peaking.
Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2
Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3
Vista de pagina 78
1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 90 91

Comentarios a estos manuales

Sin comentarios