Cirrus-logic CS4265 Manual de usuario Pagina 1

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com104 dB, 24-Bit, 192 kHz Stereo Audio CODECD/A Features Multi-Bit Delta S

10 DS657F3CS4265DAC ANALOG CHARACTERISTICSTest Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25

DS657F3 11CS42656. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance andmaximum capacitance required for the in

12 DS657F3CS4265 AOUTxAGND3.3µFVoutRLCLFigure 1. DAC Output Test Load Figure 2. Maximum DAC Loading1005075252.551015Safe OperatingRegionCapaci

DS657F3 13CS4265ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25

14 DS657F3CS426511. Valid when the line-level inputs are selected.DC AccuracyGain Error --10 %Gain Drift - 100 - ppm/°CLine-Level Input Characterist

DS657F3 15CS4265ADC ANALOG CHARACTERISTICS (Continued) 12. Referred to the typical line-level full-scale input voltage13. Valid for Double- and Qu

16 DS657F3CS4265ADC DIGITAL FILTER CHARACTERISTICS 15. Filter response is guaranteed by design.16. Response shown is for Fs = 48 kHz. 17. Resp

DS657F3 17CS4265DC ELECTRICAL CHARACTERISTICSAGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.18. Power

18 DS657F3CS4265DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.21. Ser

DS657F3 19CS4265SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTLogic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 23) 23. See Figures 3 an

2 DS657F3CS4265System Features Synchronous IEC60958-3 Transmitter– Up to 192 kHz Sampling Rates– 75  Drive Capability Serial Audio Data Input Multi

20 DS657F3CS4265 sdistslrtSDOUTSCLKOutputLRCKOutputSDINsdotsdihtsdistslrtSDOUTSCLKInputLRCKInputSDINsdotsdihtsclkhtsclkltsclkwtFigure

DS657F3 21CS4265 Figure 5. Format 0, Left-Justified up to 24-Bit DataLRCKSCLK SDATA+3 +2 +1+5 +4-1 -2 -3 -4 -5+3 +2 +1+5 +4MSB-1 -2 -3 -4Channel A -

22 DS657F3CS4265SWITCHING CHARACTERISTICS - I²C CONTROL PORTInputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.24. Data must be held for suff

DS657F3 23CS42653. TYPICAL CONNECTION DIAGRAMVLS10 µF+3.3V to +5V47 µFVQFILT+0.1 µF10 µF0.1 µF10 µF0.1 µF+1.8Vto +5VDGNDVLC0.1 µF+1.8Vto +5VSCLSDARST2

24 DS657F3CS42654. APPLICATIONS4.1 Recommended Power-Up Sequence1. Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, th

DS657F3 25CS4265In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK ratio to achieve a post-divider MCLK/LR

26 DS657F3CS4265which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-tichannel system.The high

DS657F3 27CS42654.4 Analog Input Multiplexer, PGA, and Mic GainThe CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable

28 DS657F3CS4265topology. If pseudo-differential input functionality is not required, simply connect the SGND pin to AGND through the parallel combina

DS657F3 29CS4265clocking change, the DAC outputs will always be in a zero-data state. If non-zero serial audio input is present at the time of switchi

DS657F3 3CS4265TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS657F3CS42654.11 Mute ControlThe MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK to LRCK ratio isincorrect, an

DS657F3 31CS4265under the control of a register bit. The CS4265 also allows immediate muting of the IEC60958-3 transmit-ter audio data through a contr

32 DS657F3CS4265Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 16, the write operati

DS657F3 33CS42654.15 ResetWhen RESET is low, the CS4265 enters a low-power mode and all internal states are reset, including thecontrol port and regis

34 DS657F3CS42655. REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5 4 3 2 1 001h Ch

DS657F3 35CS426511h Transmitter Control 1Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved0000 0 0 0 012h Transmitter Control 2Tx_DIF1 T

36 DS657F3CS42656. REGISTER DESCRIPTION6.1 Chip ID - Register 01hFunction:This register is Read-Only. Bits 7 through 4 are the part number ID, which i

DS657F3 37CS42656.2.4 Power-Down DAC (Bit 1)Function:The DAC pair will remain in a reset state whenever this bit is set.6.2.5 Power-Down Device (Bit 0

38 DS657F3CS42656.3.3 De-Emphasis Control (Bit 1)Function:The standard 50/15 s digital de-emphasis filter response, Figure 17, may be implemented for

DS657F3 39CS42656.4.3 Mute ADC (Bit 2)Function:When this bit is set, the serial audio output of the both ADC channels is muted.6.4.4 ADC High-Pass Fil

4 DS657F3CS42656.3.1 DAC Digital Interface Format (Bits 5:4) ... 376.3.

40 DS657F3CS42656.6 Signal Selection - Address 06h6.6.1 DAC SDIN Source (Bit 7)Function:This bit is used to select the serial audio data source for th

DS657F3 41CS42656.9 ADC Input Control - Address 09h6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)Function:Soft Ramp EnableSoft Ramp allows level

42 DS657F3CS42656.11 DAC Channel B Volume Control - Address 0Bh6.11.1 Volume Control (Bits 7:0)Function:The digital volume control allows the user to

DS657F3 43CS4265ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-itored and implemented for ea

44 DS657F3CS42656.14 Status Mask - Address 0EhFunction:The bits of this register serve as a mask for the Status sources found in the register “Status

DS657F3 45CS42656.18 Transmitter Control 2 - Address 12h6.18.1 Transmitter Digital Interface Format (Bits 7:6)Function:The required relationship betwe

46 DS657F3CS42656.18.7 Mono Mode Channel Selection (Bit 0)Function:When this bit is cleared, channel A input data will be transmitted in both channel

DS657F3 47CS42657. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

48 DS657F3CS42658. DAC FILTER PLOTS Figure 18. DAC Single-Speed Stopband Rejection Figure 19. DAC Single-Speed Transition Band0 0.05 0.1 0.15

DS657F3 49CS4265 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-0. 2-0. 100.10.20.30.40.50.60.70.8Frequency (normalized to Fs)Amplitud

DS657F3 5CS426511.1.1 Accessing the E Buffer ...

50 DS657F3CS42659. ADC FILTER PLOTS Figure 30. ADC Single-Speed Stopband Rejection Figure 31. ADC Single-Speed Stopband RejectionFigure 32. AD

DS657F3 51CS4265 Figure 36. ADC Double-Speed Transition Band (Detail) Figure 37. ADC Double-Speed Passband RippleFigure 38. ADC Qua

52 DS657F3CS426510.EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS This section details the external components required to interface the IEC60958-3 transm

DS657F3 53CS426511.CHANNEL STATUS BUFFER MANAGEMENTThe CS4265 has a comprehensive channel status (C) data buffering scheme which allows the user to ma

54 DS657F3CS426511.1.1 Accessing the E BufferThe user can monitor the data being transferred by reading the E buffer, which is mapped into the registe

DS657F3 55CS426511.3.1 One-Byte ModeIn many applications, the channel status blocks for the A and B channels will be identical. In this situation, if

56 DS657F3CS426512.PACKAGE DIMENSIONSNotes:1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies to the plated termin

DS657F3 57CS426514.ORDERING INFORMATION 15.REVISION HISTORYProduct Description Package Pb-Free Grade Temp Range Container Order #CS426524-bit, 1

6 DS657F3CS4265Figure 42.Consumer Output Circuit (VD = 5 V) ...

DS657F3 7CS42651. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDA 1 Serial Control Data (Input/Output) - Bidirectional data line for the I²C control

8 DS657F3CS4265VA 17 Analog Power (Input) - Positive power for the internal analog section.AGND 18 Analog Ground (Input) - Ground reference for the in

DS657F3 9CS42652. CHARACTERISTICS AND SPECIFICATIONSSPECIFIED OPERATING CONDITIONSAGND = DGND = 0 V; All voltages with respect to ground.Notes: 1. Max