Cirrus-logic CS8427 Manual de usuario descargar pdf (Pagina 11)

CS8427

DS477F5 11

2. TYPICAL CONNECTION DIAGRAM

* A separate analog supply is only necessary in applications where RMCK is used

for a jitter sensitive task. For applications where RMCK is not used for a jitter

sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling

capacitor between VA+ and AGND.

CS8427

Cable

Termination

RXP

RXN

AES3/

SPDIF

Source

3-wire Serial

Audio Source

ILRCK

ISCLK

SDIN

Clock Source

and Control

RMCK

OMCK

Hardware

Control

RST

RERR

EMPH

TCBL

To other

CS8427's

Cable

Interface

AES3/

SPDIF

Equipment

TXP

TXN

3-wire Serial

Audio Input

Device

OLRCK

OSCLK

SDOUT

Microcontroller

SDA/CDOUT

AD0/CS

SCL/CCLK

AD1/CDIN

INT

VA+ V L +

Ferrite *

Bead

+5.0 V

Analog

Supply*

0.1 Fμ

DGNDFILTAGND

RFILT

CFILT CRIP

H/S

+3.3 V or +5.0 V

Digital Supply

DA2/

Figure 5. Recommended Connection Diagram for Software Mode

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 59 60

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 4
LIST OF TABLES 4
ABSOLUTE MAXIMUM RATINGS 5
TRANSMITTER CHARACTERISTICS 6
SWITCHING CHARACTERISTICS 7
Figure 3. SPI Mode timing 9
Figure 4. I²C Mode timing 10
2. TYPICAL CONNECTION DIAGRAM 11
3. GENERAL DESCRIPTION 12
3.1 Audio Input/Output Ports 12
3.2 Serial Control Port 12
Documents 13
14 DS477F5 14
DS477F5 15 15
16 DS477F5 16
6.5 User Data Handling 17
6.6 Non-Audio Auto Detection 17
7. AES3 TRANSMITTER 18
Status Boundary Timing 18
7.2 TXN and TXP Drivers 18
8. MONO MODE OPERATION 19
8.1 Receiver Mono Mode 19
8.2 Transmitter Mono Mode 19
20 DS477F5 20
22 DS477F5 22
Channel A Channel B 23
Channel A 23
Channel B 23
Frame 191 24
DS477F5 25 25
26 DS477F5 26
7 6 543210 27
11.1 Control 1 (01h) 28
11.2 Control 2 (02h) 28
11.3 Data Flow Control (03h) 29
11.9 Interrupt 1 Mask (09h) 33
11.11 Interrupt 2 Mask (0Ch) 34
13. HARDWARE MODE DESCRIPTION 42
46 DS477F5 46
16. PACKAGE DIMENSIONS 47
17. ORDERING INFORMATION 49
50 DS477F5 50
18.3 AES3 Receiver External 51
Components 51
USER DATA BUFFER MANAGEMENT 52
Management 52
DS477F5 53 53
Two Byte mode 54
19.2.2 Mode 2: Block Mode 54
20.APPENDIX C: PLL FILTER 55
20.1 General 55
20.2.1 General 56
20.2.2 Capacitor Selection 56
20.2.3 Circuit Board Layout 56
20.3.4 Jitter Tolerance 58
20.3.5 Jitter Attenuation 59
21. REVISION HISTORY 60

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Cirrus-logic CS8427 Manual de usuario Pagina 11

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