Cirrus-logic CS8422 Manual de usuario Pagina 1

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digit

10 DS692F2CS8422XTI 11Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock” on page 38 for more deta

DS692F2 11CS84221.2 Hardware Mode Pin Name Pin # Pin DescriptionRXP/RXN[1:0]1256AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3

12 DS692F2CS8422MCLK_OUT 13Buffered MCLK (Output) - Buffered output of XTI clock. If a 20 k pull-up resistor to VL is present on this pin, the SRC MC

DS692F2 13CS84222. CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi

14 DS692F2CS8422PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTERXTI-XTO = 24.576 MHz; Input signal = 1.000 kHz, Measurement Bandwidth = 20 to Fso/2

DS692F2 15CS8422DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Notes:3. Power-Down Mode is defined as RST = LOW w

16 DS692F2CS8422DIGITAL INTERFACE SPECIFICATIONSAGND = DGND = 0 V; all voltages with respect to 0 V.Notes:5. When a digital signal is sent to the AES

DS692F2 17CS8422SWITCHING SPECIFICATIONSInputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Parameter Symbol Min Typ Max UnitsRST pin Low Pulse Width (

18 DS692F2CS8422Notes:7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.8. If ISCLK is selected

DS692F2 19CS84229. Typical base band jitter in accordance with AES-12id-2006 section 3.4.2. Measurements are Time In-terval Error (TIE) taken with 3rd

2 DS692F2CS8422System Features SPI™ or I²C™ Software Mode and Stand-Alone Hardware Mode Flexible 3-wire Digital Serial Audio Input Port Dual Serial

20 DS692F2CS8422SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.Notes:13. tspi only needed before

DS692F2 21CS8422SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.Notes:17. Data must be held for s

22 DS692F2CS84223. TYPICAL CONNECTION DIAGRAMS 3.1 Software Mode CS8422VD_FILTSerial Audio Input DeviceCrystal/Clock Source MicrocontrollerSerial Audi

DS692F2 23CS84223.2 Hardware Mode CS8422VD_FILTSerial Audio Input DeviceAES3/SPDIF/IEC60958 Receiver CircuitryTDM Output DeviceRXP01RXN02RXP15RXN16AGN

24 DS692F2CS84224. OVERVIEWThe CS8422 is a 24-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter with inte-grated digita

DS692F2 25CS84225.1 Serial Port Clock Operation5.1.1 Master ModeWhen a serial port is set to master mode, its left/right clock (ILRCK, OLRCK1, or OLRC

26 DS692F2CS8422 I/OLRCKI/OSCLKMSB LSBMSBLSBChannel ASDINSDOUTMSBChannel BFigure 9. Serial Audio Interface Format – I²SMSB LSBMSBLSBMSBI/OLRCKI/OSCLK

DS692F2 27CS84225.1.5 Time Division Multiplexing (TDM) ModeTDM Mode allows several TDM-compatible devices to be serially connected together allowing t

28 DS692F2CS8422 OLRCKOSCLKSDOUT/TDM_INMSB32 OSCLKsSDOUT 4, ch A32 OSCLKsSDOUT 4, ch B32 OSCLKsSDOUT 3, ch A32 OSCLKsSDOUT 3, ch B32 OSCLKsSDOUT 2, c

DS692F2 29CS84226. DIGITAL INTERFACE RECEIVERThe CS8422 includes a digital interface receiver that can receive and decode audio data according to the

DS692F2 3CS8422TABLE OF CONTENTS1. PIN DESCRIPTION ...

30 DS692F2CS84226.2.2.1 Single-Ended Input ModeWhen the receiver input multiplexer is set to Single-Ended Mode, the receiver inputs can be switched be

DS692F2 31CS8422 Figure 18. Differential Receiver Input Structure6.3 Recovered Master Clock - RMCKThe CS8422 has an internal PLL which recovers a hig

32 DS692F2CS8422frequencies will be derived from the XTI-XTO clock when clock switching has taken place and the RMCK-to-LRCK ratio will be maintained.

DS692F2 33CS8422The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error andwill remain set until the us

34 DS692F2CS8422If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS® data transmission, aninternal AUTODETECT signal will

DS692F2 35CS84226.10.2 Software Mode ControlIn Software Mode, several options are available for accessing the Channel Status and User data that isenco

36 DS692F2CS8422 RCBL (out)VLRCK (out)C/U (out)C/U[0] C/U[1] C/U[383]t t192 AES3 FramesFigure 19. C/U Data OutputsNote:1. RCBL will go high on the tr

DS692F2 37CS84227. SAMPLE RATE CONVERTER (SRC)Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a

38 DS692F2CS84227.3 SRC MutingThe SDOUT pin sourced by the SRC (SDOUT1 or SDOUT2 in Software Mode, SDOUT1 in HardwareMode) is set to all zero output (

DS692F2 39CS8422oscillator provides the clock to run all of the internal logic. See Section 7.4.1 and Section 7.4.2 for explana-tion of how the SRC MC

4 DS692F2CS84226.10.2 Software Mode Control ... 3

40 DS692F2CS8422RXP/RXN0RXP/RXN1Receiver Clock Recovery (PLL)Sample Rate ConverterSerial Audio Output2OLRCK1OSCLK1SDOUT1TDM_IN1OLRCK2OSCLK2SDOUT2Seria

DS692F2 41CS8422Table 3. Hardware Mode Control Settings8.1 Hardware Mode Serial Audio Port ControlThe CS8422 uses the resistors attached to the MS_SEL

42 DS692F2CS8422determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in thehardware control pin descriptions

DS692F2 43CS84229. SOFTWARE MODE CONTROL9.1 Control Port DescriptionThe control port is used to access the registers, allowing the CS8422 to be confi

44 DS692F2CS84229.1.2 I²C ModeIn I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no CS

DS692F2 45CS842210.REGISTER QUICK REFERENCEThis table shows the register names and default values for read-write registers.AddrFunction7654321001h Chi

46 DS692F2CS842211h Receiver Chan-nelStatusAUX3 AUX2 AUX1 AUX0 PRO COPY ORIG EMPH12h Format Detect StatusPCM IEC61937 DTS_LD DTS_CD HD_CD DGTL_SIL Res

DS692F2 47CS84222Ch Channel B Sta-tus Byte 4BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0]2Dh Burst Preamble PC Byte 0PC0[7] PC0[6] PC0[5] PC

48 DS692F2CS842211.SOFTWARE REGISTER BIT DEFINITIONSThe table row beneath the row that contains the register-bit name shows the register bit default v

DS692F2 49CS842201 - Active low, low output indicates an interrupt condition has occurred.10 - Open drain, active low. Requires an external pull-up re

DS692F2 5CS842212.4.3 Serial Copy Management System (SCMS) ... 6912.5 Jitter Att

50 DS692F2CS842201 - replace the current audio sample with all zeros (mute).10 - do not change the received audio sample.11 - reservedCHS – Sets which

DS692F2 51CS842211.5 GPO Control 1 (05h)GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See Table 7 for available outputs forGPO[3:0]. 11.6 G

52 DS692F2CS84220000 - ILRCK = MCLK/640001 - ILRCK = MCLK/960010 - ILRCK = MCLK/1280011 - ILRCK = MCLK/1920100 - ILRCK = MCLK/2560101 - ILRCK = MCLK/3

DS692F2 53CS84220 - XTI-XTO1 - RMCKSRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See “SRC Mas-ter Clock” on p

54 DS692F2CS842211.10 Data Routing Control(0Ah)SDOUT1[1:0] - Controls the data source for SDOUT100 - Sample Rate Converter01 - AES3 Receiver Output10

DS692F2 55CS8422SIFSEL[2:0] - Serial audio input data format000 - Left-Justified, up to 24-bit data001 - I²S, up to 24-bit data010 - Right-Justified,

56 DS692F2CS8422SORES1[1:0] - Resolution of the output data on SDOUT00 - 24-bit resolution.01 - 20-bit resolution.10 - 18-bit resolution.11 - 16-bit r

DS692F2 57CS8422SORES2[1:0] - Resolution of the output data on SDOUT00 - 24-bit resolution.01 - 20-bit resolution.10 - 18-bit resolution.11 - 16-bit r

58 DS692F2CS842211.15 Interrupt Unmasking (0Fh)The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1,

DS692F2 59CS84221000 - Auxiliary data is 8 bits long.1001 - 1111 ReservedPRO - Channel status block format indicator0 - Received channel status block

6 DS692F2CS8422Figure 40.Wideband FFT – 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ...

60 DS692F2CS8422interrupt mode is set to level active and the error source is still true. Bits that are masked off in the receivererror mask register

DS692F2 61CS8422Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format DetectStatus register goes high, it

62 DS692F2CS842296KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi  49 kHz orFsi  120 kHz, this bit will o

DS692F2 63CS84221 - There has been at least one biphase error associated with incoming AES3 data during the input of thelast AES3 data block.BLK_PERR

64 DS692F2CS8422Each byte is MSB first with respect to the 80 Channel Status bits. Thus bit 0 of address 23h, AC0[0], is thelocation of the Pro bit. F

DS692F2 65CS842212.APPLICATIONS12.1 Reset, Power Down, and Start-Up When RST is low the CS8422 enters a low power mode, all internal states are reset,

66 DS692F2CS8422boxes held to the same potential, and the cable shield might be depended upon to make that electrical con-nection. Generally, it is a

DS692F2 67CS842212.3.2 Isolating Transformer RequirementsPlease refer to the application note AN134: AES and SPDIF Recommended Transformers for resour

68 DS692F2CS8422There are a number of conditions that will inhibit the buffer update. If the CS_UPDATE bit in “Receiver Sta-tus (16h)” is set to ‘0’,

DS692F2 69CS842212.4.3 Serial Copy Management System (SCMS)In Software Mode, the CS8422 allows read access to all the channel status bits. For consume

DS692F2 7CS8422Figure 67.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 32 kHz ...

70 DS692F2CS842212.6 Jitter ToleranceThe CS8422 is compliant to the jitter tolerance requirements set forth in the AES-3 and IEC60958-4 speci-fication

DS692F2 71CS842213.PERFORMANCE PLOTS Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to Fso/2 Hz (unweighted);VA = VL = V

72 DS692F2CS8422-200+0-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS5k 45k10k 15k 20k 25k 30k 35k 40kHz-200+0-190-180-170-160

DS692F2 73CS8422-200+0-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS2.5k 22.5k5k 7.5k 10k 12.5k 15k 17.5k 20kHz-200+0-190-180

74 DS692F2CS8422-200+0-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS5k 45k10k 15k 20k 25k 30k 35k 40kHz-200+0-190-180-170-160

DS692F2 75CS8422-200+0-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS40k 180k60k 80k 100k 120k 140k 160kHz-200+0-190-180-170-1

76 DS692F2CS8422-200+0-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS40k 180k60k 80k 100k 120k 140k 160kHz-200+0-190-180-170-1

DS692F2 77CS8422-140+0-135-130-125-120-115-110-105-100-95-90-85-80-75-70-65-60-55-50-45-40-35-30-25-20-15-10-5dBFS-14 0 +0-120 -100 -80 -60 -40 -20dBF

78 DS692F2CS8422-180-100-175-170-165-160-155-150-145-140-135-130-125-120-115-110-105dBFS-14 0 +0-120 -100 -80 -60 -40 -20dBFS-180-100-175-170-165-160-

DS692F2 79CS8422-180-100-175-170-165-160-155-150-145-140-135-130-125-120-115-110-105dBFS0 20k2k 4k 6k 8k 10k 12k 14k 16k 18kHz-180-100-175-170-165-160

8 DS692F2CS8422LIST OF TABLESTable 1. VLRCK Behavior ...

80 DS692F2CS842214.PACKAGE DIMENSIONS Notes:1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies to the plated termi

DS692F2 81CS842216.ORDERING INFORMATION17.REFERENCES1. Audio Engineering Society AES3-2003: “AES standard for digital audio - Digital input-output int

82 DS692F2CS842218.REVISION HISTORY Release ChangesF1 Final Release.Changed VA, VREG, and VL = 5.0 V normal operation values in DC Electrical Characte

DS692F2 9CS84221. PIN DESCRIPTION1.1 Software Mode Pin Name Pin # Pin DescriptionRX[3:0],RXP/RXN[1:0]1256AES3/SPDIF Input (Input) - Single-ended or di