Cirrus-logic CS8422 Manual de usuario Pagina 75
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DS692F2 75
CS8422
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Figure 62. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 48 kHz
Figure 63. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 96 kHz
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Figure 64. THD+N vs. Output Sample Rate –
0dBFS 1kHzTone, Fsi=44.1kHz
Figure 65. Dynamic Range vs. Output Sample Rate –
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Figure 66. THD+N vs. Output Sample Rate –
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Figure 67. Dynamic Range vs. Output Sample Rate –
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- Features 1
- System Features 2
- General Description 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 5
- LIST OF TABLES 8
- 1. PIN DESCRIPTION 9
- 10 DS692F2 10
- 1.2 Hardware Mode 11
- 12 DS692F2 12
- ABSOLUTE MAXIMUM RATINGS 13
- 0.5465*Fso 14
- (Note 3) 15
- (Note 4) 15
- SWITCHING SPECIFICATIONS 17
- (output) 19
- 3.1 Software Mode 22
- 3.2 Hardware Mode 23
- 4. OVERVIEW 24
- 5.1.1 Master Mode 25
- 5.1.2 Slave Mode 25
- 5.1.3 Hardware Mode Control 25
- 5.1.4 Software Mode Control 25
- Channel A Channel B 26
- LSB MSB V U C Z 26
- MSB V U C Z 26
- 5.1.5.1 TDM Master Mode 27
- 5.1.5.2 TDM Slave Mode 27
- 5.1.5.3 Hardware Mode Control 27
- 5.1.5.4 Software Mode Control 27
- OLRCK OSCLK SDOUT 28
- 6. DIGITAL INTERFACE RECEIVER 29
- 6.3.1 Hardware Mode Control 31
- 6.3.2 Software Mode Control 31
- 6.4 XTI System Clock Mode 31
- 6.4.1 Hardware Mode Control 32
- 6.4.2 Software Mode Control 32
- 6.5 AES11 Behavior 32
- 6.6.1 Software Mode 32
- 6.6.2 Hardware Mode Control 33
- 6.7 Non-Audio Detection 33
- 6.10.2 Software Mode Control 35
- 7.1.1 Hardware Mode Control 37
- 7.1.2 Software Mode Control 37
- 7.2 SRC Locking 37
- 7.3 SRC Muting 38
- 7.4 SRC Master Clock 38
- 8. HARDWARE MODE CONTROL 39
- 9. SOFTWARE MODE CONTROL 43
- 9.1.2 I²C Mode 44
- 10.REGISTER QUICK REFERENCE 45
- 46 DS692F2 46
- Addr Function 7 6 5 4 3 2 1 0 46
- DS692F2 47 47
- AddrFunction76543210 47
- 11.2 Clock Control (02h) 48
- Reserved Reserved 49
- 00010000 49
- 00000100 49
- 11.5 GPO Control 1 (05h) 51
- 11.6 GPO Control 2 (06h) 51
- 01000000 52
- 00001——— 53
- 00000——— 54
- 76543210 55
- —0000000 57
- 11.16 Interrupt Mode (10h) 58
- 11.19 Receiver Error (13h) 59
- 11.20 Interrupt Status (14h) 60
- 11.21 PLL Status (15h) 61
- 11.22 Receiver Status (16h) 62
- 12.APPLICATIONS 65
- TTL/CMOS 66
- Twisted 67
- 12.4.2 Accessing the E buffer 68
- 12.5 Jitter Attenuation 69
- 12.6 Jitter Tolerance 70
- 12.7 Group Delay 70
- 13.PERFORMANCE PLOTS 71
- 72 DS692F2 72
- DS692F2 73 73
- 74 DS692F2 74
- DS692F2 75 75
- 76 DS692F2 76
- DS692F2 77 77
- 78 DS692F2 78
- DS692F2 79 79
- 14.PACKAGE DIMENSIONS 80
- 16.ORDERING INFORMATION 81
- 17.REFERENCES 81
- 18.REVISION HISTORY 82
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