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16-6 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
*
+0.23% Sample Frequency Error
**
Optional 12.288 MHz external clock
MCLK(BUZ) will always output 256 Fs on pin 93 for internal or external clocks used.
MCLK(BUZ) is also referred to as MCLKOUT in the datasheet. For details on the
hardware interface for the DAI and creatingMCLK for external CODECs,pleaserefer
to application note APP199, “DAI Interface for Playing MP3 Music” (AN199)
Programming the DAI Control and Data Registers
Once the DAI machine has been selected (DAI64FS register), the mode(128/64 Fs)
must be determined based on the external CODECs used. If 64 Fs is selected, 128 Fs
must be deselected. The converse is also required. The register 64DAIFS enables
128/64 Fs mode along with SYSCON3. Both registers must be programmed to set or
clear these options.
In 64 Fs mode, the ECS bit in the DAIR control register must be set regardless of the
source for
MCLK.For128Fs,thebitisnotread.
For both modes, the 64DAIFS register will always select the audio clock source and
program the audio divider. See the register tables for more information. Details for
programming the DAI FIFOs and interrupts for digital audio applications can be
found in application note APP199,“DAI Interface for Playing MP3 Music”
(AN199REV1)
The DAI FIFOs in the DAIDR2 register must be enabled and to generate an interrupt
based on the condition of the FIFOs, the DAIINT bit in the INTRM3 register must be
set along with the appropriate mask from the DAI Control Register. This will insure
an FIQ interrupt will occur. The interrupt can be cleared by writing 0xFFFFFFFF to
the DAISR register.
Table 16-6: Programmable Audio Divisors at 90 MHz
Clock
Source (MHz)
Sample
Frequency (kHz)
128 Fs
Audio Bit Clock
(MHz)
64 Fs
Audio Bit Clock
(MHz)
128/64 Fs
Divisor
(AUDIV)
*
90.3168
8 1.024 0.512 44
*
90.3168
11.025 1.4112 0.7056 32
**
12.288
12 1.536 0.786 8
*
90.3168
16 2.048 1.024 22
*
90.3168
22.05 2.8224 1.4112 16
**
12.288
24 3.072 1.536 4
*
90.3168
32 4.096 2.048 11
*
90.3168
44.1 5.6448 2.8224 8
**
12.288
48 6.144 3.072 2
- EP73xx User’s Guide 1
- 1Contents 4
- Chapter 5. System Registers 5
- Chapter 6. Processor Support 6
- Chapter 7. SDRAM Controller 6
- Chapter 9. LCD Interface 6
- Appendix A. Boot Code 8
- Contents 9
- List of Figures 10
- List of Tables 12
- Chapter 1 15
- 1Introduction 15
- Overview 15
- Memory Map and Register List 16
- Internal Register Map 17
- Pin Description 20
- External Signal Functions 21
- Output Bi-Directional Pins 24
- Block Diagrams 25
- References 26
- Chapter 2 27
- 2CPU Core 27
- Programming Register List 27
- Programming Examples 28
- CPU Core 29
- Write Buffer 32
- CPU Register Definitions 33
- User FIQ IRQ SVC Undef Abort 34
- CPU Clocks 35
- On-Chip PLL 36
- PLL Register Descriptions 37
- CPU State Control 38
- Idle State 39
- Power Up Sequence 40
- Table 3-1: Timer Registers 43
- Timer Register Descriptions 45
- Chapter 4 47
- 4Interrupt Controller 47
- Interrupt Register List 47
- Interrupt Operation 50
- Interrupt Listing 51
- Operating State 52
- Standby State 53
- Interrupt Controller 54
- End-Of-Interrupt Locations 59
- Chapter 5 61
- 5System Registers 61
- System Register List 62
- MaverickKey 64
- Unique-ID 64
- BUZ output reflects 65
- EXPCLK is 66
- System Registers 68
- 0032-bit 71
- 1016-bit 71
- 11Reserved 71
- CLKSEL (PE[2])input,latched 72
- Chapter 6 75
- 6Processor Support 75
- Internal Boot Mode 76
- External Boot Mode 76
- CS0 and the 77
- Endianess 78
- Endian Byte Addressing 79
- Processor Support 80
- Chapter 7 81
- 7SDRAM Controller 81
- SDRAM Register List 81
- SDRAM Register Descriptions 83
- SDRAM Controller 84
- SRAM/Expansion Bus Controller 89
- Chapter 9 91
- 9LCD Interface 91
- LCD Register List 91
- LCD DMA Controller 93
- Gray Scale 94
- 4 Bits per pixel 95
- 2 Bits per pixel 95
- 1 Bit per pixel 95
- Hardware Interface 96
- Color LCDs 96
- LCD Register Descriptions 97
- (PALMSW) 98
- FBADDR) 99
- LCD Interface 100
- Operational Overview 102
- Keyboard Interface 103
- Chapter 11 105
- 11General Purpose I/O (GPIO) 105
- Introduction 105
- Features 105
- Programming Example 106
- Register Descriptions 106
- Chapter 12 107
- 12PWM Interface 107
- Block Diagram 107
- PWM Register Descriptions 109
- PWM Interface 110
- PD0 / LEDFLSH)tobetoggledata 111
- Register Definitions 112
- Chapter 14 113
- 14JTAG Interface 113
- Boundary Scan 114
- Debug Modes 115
- Debug/ICE Test Mode 116
- Hi-Z (System) Test Mode 116
- JTAG Interface 117
- ADCCLK) 121
- Bit Descriptions: 122
- (SYNCIO[6:0]) 123
- SSI Port 124
- Chapter 16 125
- 16DAI/CODEC/SSI2 125
- DAI/CODEC/SSI2 Register List 126
- DAI Interface 128
- DAI Clock Generation 129
- Master/Slave SSI2 Interface 131
- Read Back of Residual Data 132
- CODEC Sound Interface 134
- DAI Registers 135
- DAI Control Register (DAIR) 136
- Full Bit Descriptions 137
- DAI Data Register 0 (DAIDR0) 138
- DAI Data Register 1 (DAIDR1) 139
- DAI Data Register 2 (DAIDR2) 140
- DAI Status Register (DAISR) 140
- DAI/CODEC/SSI2 141
- SSI2 Registers 144
- CODEC Register 144
- SIR Encoder 150
- UART and SIR Encoder 153
- WRDLEN Word Length 153
- Appendix A 155
- ABoot Code 155
- Boot Code 156
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