Cirrus-logic EP73xx Manual de usuario descargar pdf (Pagina 131)

EP7309/11/12 User’s Manual - DS508UM4 16-7

DAI/CODEC/SSI2

1616

Data is read and written from the DAI data register for both the left and right

channels. The internal FIFOs for both channel shift the data accordingly to proper

reads from the system, and writes to the system.

Master/Slave SSI2 Interface

A second SPI/Microwire interface with full master/slave capability is provided by

the EP73XX. Data rates in slave mode are theoretically up to 512 kbits/s, full duplex,

although continuous operation at this data rate will give an interrupt rate of 2 kHz,

which is too fast for many operating systems. This would require a worst-case

interruptresponsetimeoflessthan0.5msandwouldcauselossofdatathroughTX

underruns and RX overruns.

The interface is fully capable of being clocked at 512 kHz when in slave mode.

However, it is anticipated that external hardware will be used to frame the data into

packets. Therefore, although the data would be transmitted at a rate of 512 kbits/s,

the sustained data rate would in fact only be 85.3 kbits/s (i.e., 1 byte every 750 µsec).

At this data rate, the required interrupt rate will be greater than 1 ms, which is

acceptable.

There are separate half-word-wide RX and TX FIFOs (16 half-words each) and

corresponding interrupts which are generated when the FIFO’s are half-full or half-

empty as appropriate. The interruptsare called SS2RX and SS2TX, respectively.

Thereare five pins to support this SSI port:

SSIRXDA,SSITXFR,SSICLK,SSITXDA,and

SSIRXFR.TheSSICLK, SSIRXDA, SSIRXFR,andSSITXFR signals are inputs and the

SSITXDA signal is an output in slave mode. In the master mode, SSICLK, SSITXDA,

SSITXFR,andSSIRXFR are outputs,and SSIRXDA is an input. Master mode is enabled

by writing a one to the SS2MAEN bit (SYSCON2[9]). When the master/slave SSI is

not required, it can be disabled to save power by writing a zero to the SS2TXEN and

the SS2RXEN bits (SYSCON2[4] [7]). When set, these two bits independently enable

thetransmitandreceivesidesoftheinterface.

The master/slave SSI is synchronous,full duplex, and capable of supporting serial

data transfers between two nodes. Although the interface is byte-oriented, data is

loaded in blocks of two bytes at a time. Each data byte to be transferred is marked by

a frame sync pulse, lasting one clock period, and located one clock prior to the first bit

being transferred. Direction of the SSI2 ports, in slave and master mode, is shown in

Figure 16-3.

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Cirrus-logic EP73xx Manual de usuario Pagina 131