Cirrus-logic EP73xx Manual de usuario descargar pdf (Pagina 71)

EP7309/11/12 User’s Manual - DS508UM4 5-11

System Registers

URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on

thestateoftheUFIFOENbitintheUART1bitrateandlinecontrol

holding register is empty. If the FIFO is enabled,the URXFE bit

will be set when the RX FIFO is empty.

UTXFF1: UART1transmitFIFO full. The meaningof thisbitdependsonthe

state of the UFIFOEN bit in the UART1 bit rate and line control

holding register is full. If the FIFO is enabled, the UTXFF bit will

be set when the TX FIFO is full.

CRXFE: CODEC RX FIFO empty bit. This will be set if the 16-byte CODEC

RX FIFO is empty.

CTXFF: CODEC TX FIFO full bit. This will be set if the 16-byte CODEC TX

FIFO is full.

SSIBUSY: Synchronous serial interface busy bit. This bit will be set while

data is being shifted in or out of the synchronous serial interface,

when clear data is valid to read.

BOOTBIT[0-1]:These bits indicate the default (power-on reset) bus width of

the ROM interface. See Memory Configuration Registers for more

details on the ROM interface bus width. The state of these bits

reflect the state of

PE[0-1] during power on reset, as shown in the

table below.

ID: Will always read “1” for the EP73xx device

VERID: Version ID bits. These 2 bits determine the version ID for the

EP73xx. Will read “01” for the initial version.

Table 5-5: Default (Power-on Reset) Bus Width Settings

PE[1]

(BOOTBIT1)

PE[0]

(BOOTBIT0)

Boot Option

0032-bit

018-bit

1016-bit

11Reserved

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 157 158

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Cirrus-logic EP73xx Manual de usuario Pagina 71